14 Scan Compression Jobs

Position: Senior DFT Engineer Location: Bangalore / Hyderabad Experience: 5+ Years Email: karthik.adasu@proxelera.com Job Description: We are seeking an experienced Senior DFT Engineer with strong expertise in DFT design, verification, and test methodologies. Key Responsibilities: * Implement and verify DFT logic including MBIST, scan chains, compression, TAP, iJTAG, and eFuse. * Perform scan insertion, scan compression, ATPG pattern generation, and coverage analysis. * Execute MBIST insertion, simulation, and debug at RTL and gate levels. * Collaborate with silicon and test engineering teams for test plan creation and pattern generation. * Participate in post-silicon bring-up, diagnostics, ...

We’re hiring a DFT Lead with 10+ years of experience in VLSI front-end design. The role involves DFT architecture, ATPG, scan insertion, STA, timing closure, and debug. Strong scripting and communication skills are essential. Required Candidate profile Experienced DFT professional skilled in ATPG, scan insertion, and timing closure. Proven ability to lead design-for-test implementation and debugging in complex SoC environments using industry tools.

We are Silicon Labs. We are the leading provider of silicon, software and solutions for a smarter, more connected world. We hire the most innovative talent in the world to solve the industry's toughest problems, providing our customers with significant advantages in performance, energy savings, connectivity and design simplicity. Silicon Labs software and mixed signal engineering teams create solutions for customers in diverse markets including the Internet of Things, (IoT), internet infrastructure, TV tuners, as well as automotive and consumer radios. Our solutions are in products from the market leaders in home automation, electric vehicles, green technology, smart TVs and home voice contr...

Experience: 10+ years Should have worked hands-on extensively on full chip DFT design, implementation, vector generation/verification, JTAG, boundary scan and simulation. Experience with Scan, Compression, ATPG and simulations with Mentor/Synopsys/Cadence tools. Logic BIST knowledge is a plus. Should have participated in successful tapeouts ofSoC/ASIC chips at 14nm or below and achieved test targets. Descent understanding of front-end SoC/ASIC design and implementation including Synthesis and STA. Develop/automate flows and scripts in Perl/Tcl to enhance the DFT methodologies & process Excellent problem solving and debugging skills. Proactive in nature Leading junior teams, Mentoring/Trainin...

Role Overview: You will be responsible for implementing Design for Test (DFT) techniques to ensure the quality and reliability of semiconductor products. Your primary focus will be on areas such as JTAG, ATPG, logic diagnosis, Scan compression, and MBIST/LBIST. Additionally, you will be involved in Tessent based ATPG flow, GLS, and Post-silicon-debug. Your expertise in Perl/Tcl/Python scripting will be crucial for this role. Key Responsibilities: - Utilize your strong fundamental knowledge of DFT techniques to perform Core and SOC level ATPG, ensuring Automotive grade quality. - Engage in hierarchical ATPG retargeting and Pattern release for application on ATE. - Conduct SOC and Core level T...

As a Senior Member of Technical Staff (SMTS) Silicon Design Engineer at AMD, you will be an integral part of the Circuit Technology team, focusing on DFT Methodology/Architect/RTL execution for high-speed SERDES Phys, Next-gen Memory Phys, and Die-to-Die interconnect IPs. Your responsibilities will include defining the DFX architecture for high-speed PHYs and die-to-die connectivity IP designs, RTL coding, supporting scan stitching, developing timing constraints, assisting with ATPG, and post-silicon bringup. Join a dynamic team that delivers cutting-edge IPs crucial for every SOC developed by AMD. Key Responsibilities: - Lead and define Design for Test/Debug/Yield Features specific to PHYs....

You should have a minimum of 4 years of experience in the field. You must be proficient in using Synthesis and netlist validation tools, particularly LEC and Spyglass checks, as well as scan insertion and DRC debug. It is essential to be well-versed in both Synopsys and Mentor Graphics DFT flows. Your expertise should also include experience in Scan Compression for Hierarchical and Modular EDT, ATPG, and Coverage debug, along with the ability to manage multiple clock domains and familiarity with the OCC flow. You should have practical experience in BIST and BISR insertion and Validation with SMS and MBIST Architect. Hands-on experience with JTAG, IJTAG, and SSN is required. You should be fam...

You will be responsible for driving DFT implementation in Wireless SoC chips. You will have full ownership of ATPG architecture, design, implementation, verification, and deployment to Silicon testing, collaborating with Test engineers. Your duties will also involve MBIST design, implementation, and verification for all memories in the SoC. You should be capable of generating and debugging DFT patterns on the tester. You will work closely with the design, design-verification, and backend teams to facilitate the integration and validation of the test logic in all phases of the design and backend implementation flow. To excel in this role, you are required to have 8-10 years of experience and ...

As a Senior DFT Engineer at Arms Solutions group DFT team in Bengaluru, India, you will play a crucial role in implementing DFT for test-chips and hard-macros to validate Arm's soft IP power, performance, area, and functionality within the context of a SoC. You will collaborate closely with RTL, Verification, Physical Implementation, and Test engineering teams throughout the project lifecycle, from early investigation to tape-out and silicon test/characterization on ATE. Your responsibilities will include architecting, implementing, and validating innovative DFT techniques on test-chips and hard-macros. You will insert DFT logic into SoC-style designs at the RTL and Synthesis gate levels, va...

You will be working as a DFT Engineer in Noida with the following responsibilities: Strong fundamental knowledge of DFT techniques including JTAG, ATPG, yield learning, logic diagnosis, Scan compression, IJTAG, and MBIST/LBIST. Experience in Tessent based ATPG flow, GLS, and Post-silicon-debug. Proficient in Perl/Tcl/Python scripting for automation and efficiency. Demonstrate excellent analytical and problem-solving skills. Conduct Core and SOC level ATPG to ensure Automotive grade quality. Handle Hierarchical ATPG retargeting and Pattern release for application on ATE. Execute SOC and Core level Timing/Non-timing GLS. Support silicon bring-up, diagnosis, and physical failure analysis. Facil...

As a Senior Member of Technical Staff (SMTS) Silicon Design Engineer at AMD, you will be an integral part of the Circuit Technology team, focusing on DFT Methodology/Architect/RTL execution for high-speed SERDES Phys, Next-gen Memory Phys, and Die-to-Die interconnect IPs. Your responsibilities will include defining the DFX architecture for high-speed PHYs and die-to-die connectivity IP designs, RTL coding, supporting scan stitching, developing timing constraints, assisting with ATPG, and post-silicon bringup. Join a dynamic team that delivers cutting-edge IPs crucial for every SOC developed by AMD. The ideal candidate possesses strong analytical and problem-solving skills with keen attention...

Lead the deployment of Synopsys DFT technologies across key customer projects Act as the primary point of contact, facilitating smooth communication with customers and internal teams Define and manage project schedules, tracking milestones, and deliverables Identify potential risks early, escalate issues as needed, and ensure timely resolutions Ensure projects meet schedule, quality, and customer satisfaction benchmarks Collaborate with AE and R&D teams to meet technical and functional objectives Manage multiple project executions, ensuring seamless alignment with business goals Prepare and deliver progress updates and technical presentations to stakeholders The Impact You Will Have: Guarant...

Deploying Synopsys DFT technologies on key customers designs and successfully executing the project. Acting as the focal point of contact and managing all external and internal communications across cross-functional teams. Planning and directing project schedules, identifying and escalating issues, and driving problems to resolution. Identifying and managing risks, ensuring the completion of projects on schedule and with high quality. Organizing interdepartmental activities and ensuring clear and concise communication. Working closely with internal teams (Applications Engineering, R&D) to meet customer requirements and achieve goals and targets. The Impact You Will Have: Ensure successful de...

Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation, You Are: An experienced Solutions Engineer with a proven track record in project execution and overall project management within the semiconductor industry You excel in deploying Synopsys DFT technologies on customer designs, ensuring projects are completed on schedule and with high quality You are adept at managing multiple projects simultaneously, recognizing and mitigating...