13 Silicon Bringup Jobs

You have a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. You possess 3 years of experience in architecture, hardware, digital design, and software design, along with 2 years of experience in Verilog/SystemVerilog. Your experience includes knowledge in computer architecture and digital design or Internet Protocol (IP) integration such as Peripheral Component Interconnect Express (PCIe) and Double Data Rate (DDR) memory. Ideally, you hold a Master's degree in Electrical Engineering, Computer Science, or a related field and have 4 years of experience working on Field Programmable Gate Array (FPGA) platforms or Emulation platforms with Internet Protocols (IPs) like PCIe, DDR memory, Gigabit Ethernet, and Flash. You also have experience in developing architectures for Machine Learning Accelerators and in writing or debugging Verilog/Register-Transfer Level (RTL) code for ASIC/FPGA designs, with waveform debug skills and knowledge of chip design flows. As part of this role, you will contribute to shaping the future of AI/ML hardware acceleration, particularly focusing on TPU (Tensor Processing Unit) technology that drives Google's demanding AI/ML applications. You will collaborate with a diverse team to develop custom silicon solutions that power Google's TPU, innovating products enjoyed by users worldwide. Your responsibilities will involve verifying complex digital designs, especially TPU architecture integration within AI/ML-driven systems. Your tasks will include integrating hardware and software stacks for pre-silicon validation of Google Cloud Tensor Processing Unit (TPU) projects using emulation platforms, creating custom test cases and tools, and ensuring the quality of silicon bring-up, validation, and characterization programs. Additionally, you will work on debugging issues, collaborating with various teams, and contributing to the development of tools, validation firmware, and testing infrastructure for Google Cloud data center systems. Overall, your role will focus on enabling chip features through firmware and driver stack, validating hardware and software designs, designing ASIC models for Emulation/FPGA Prototypes, optimizing RTL transformations, and improving hardware modeling accuracy. You will play a key role in driving debug discussions, coordinating hardware and software deliveries, and benchmarking performance to ensure efficient operations of Google's systems.,

Axiado is an AI-enhanced security processor company that is revolutionizing the control and management of digital systems. Founded in 2017, Axiado currently has a team of over 100 employees who are dedicated to developing cutting-edge technology. At Axiado, we believe that exceptional results are achieved through collaboration, respect, and going the extra mile. If you are passionate about disrupting the status quo, driving innovation, and making a difference in the world, we encourage you to apply for the following position. The ASIC/SoC Design position at Axiado offers you the opportunity to be part of a leading company in Smart Edge SoCs for network/systems control, management security systems, and IIoT. As an ASIC/SoC Design Engineer, you will be involved in all aspects of the SoC design flow, working closely with various teams and reporting to the Director of Engineering. **KEY RESPONSIBILITIES** - Developing the design and implementation of SoCs. - Micro-architecture design, RTL coding, synthesis, timing closure, and documentation of various RTL blocks. - Performance, bandwidth, and power optimization at both top-level and block-level. - Collaborating with FPGA engineers for early prototyping. - Supporting test program development, chip validation, and chip life until production maturity. - Working with firmware, software, DV, FPGA, DFT, SoC integration, and backend teams throughout different stages of ASIC development. **Qualifications** - 8+ years of experience in RTL logic design, verification, synthesis, and timing optimization. - Proficiency in writing clear micro-architecture specifications and efficient RTL code in Verilog. - Knowledge of assertions, coverage analysis, RTL synthesis, and timing closure. - Experience with interface protocols like PCIe, USB, Ethernet, DDR3/4, LPDDR, I2C/I3C, SPI, SD/SDIO/eMMC, UART, etc. - Design bring up and debug experience on FPGA-based emulation platforms. - Proficiency in scripting languages such as Perl and Python. - Previous tapeout experience is a must. - Silicon bring-up and debug experience (Preferred). - Familiarity with repository management tools like Bitbucket/Jenkins and bug tracking tools like JIRA. Axiado is dedicated to attracting, developing, and retaining top talent in a diverse and dynamic environment. Headquartered in Silicon Valley, we have access to leading research, technology, and talent. We are focused on building a team that is committed to securing every node on the internet and solving real-world problems. We value persistence, intelligence, curiosity, hard work, continuous learning, and mutual support in our team members.,

Join NVIDIA, a trailblazer at the forefront of graphics and artificial intelligence performance, efficiency, and innovation. From our roots as a groundbreaking graphic company, we have evolved into a global leader in artificial intelligence, continuously pushing the boundaries to tackle complex challenges across diverse industries. NVIDIA Silicon Solutions Group is seeking a versatile Hardware engineer to be part of the SSG Prod - System Integration Team (SIT). The SSG team is uniquely positioned to have an end-to-end view of the product development cycle - from early arch definition through bringup to product release. Our Prod arm is a hub for all GPU & SOC - silicon and system-level feature bringup, debug, validation and productization. The sophisticated nature of various chip features poses many exciting debugging situations. Someone with solid understanding and innovative thinking is required for on time release of the products. As part of the Silicon Solutions Team, we are responsible for productizing NVIDIA's chips into groundbreaking consumer, professional, server, mobile, and automotive solutions. What you will be doing: Understand various HW/SW features related to clocks, DVFS , perf, power, performance, controllers, and circuits. Productize and integrate system level features, controllers, power management & clocking techniques and policies to optimize product performance and power while meeting product release roadmap and timelines. Lead system level feature design, productization, debug and deployment - to address functional, perf, power, and productization needs for NVIDIA's silicon designs. Collaborate with ArchDev , ASIC, SW/FW, validation, and production teams throughout product life cycle Develop bringup, validation, qualification, tuning, and productization plans. Support silicon bring-up, validation and debug Coordinate product level feature deployment/debug Lead efforts and craft WARs/solutions to address customer, manufacturing, productization and bringup issues. Responsible for the GPU and SoC system qualification including feature checks, system stress at PVT conditions and debug of issues affecting any unit of the chip or software. Build supporting tools/script/infrastructure with relevant stakeholder teams. Continuously optimize validation and productization processes and methodologies to improve overall quality and efficiency. What we need to see: BTech/BE or MTech/ME degree in Electronics or equivalent experience 5+ Years of experience in silicon bringup, system level design, validation, power/performance optimization and related areas. Deep understanding of SW/firmware and HW/SW interaction Hands-on lab experience with silicon bringup, lab debug and lab tools (oscilloscopes, multimeters, logic analyzers) is preferred. Strong fundamentals in board and system design, digital design, DVFS, control systems, signal integrity, timing, clocking, power, noise, high-speed IO & buses and micro architecture. Basic programming experience such as C/C++, Python, Perl in Windows/Linux environment. Excellent problem solving, teamwork, and interpersonal skills. Excellent data analysis and logical reasoning skills. Must be a standout colleague and ready to work with global teams from diverse cultural backgrounds Why NVIDIA It's not just technology, though! It is our people, some of the brightest in the world. At the center of NVIDIA's culture are our core values, like innovation, perfection, determination, and teamwork, that guide us to be the best we can be. We offer a dynamic work environment where your contributions will directly impact the company's success. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform crucial job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation. #LI-Hybrid

As a Staff Systems Engineer at Synaptics, you will play a crucial role in our Bluetooth systems design team, collaborating closely with RF systems, MAC systems, and software teams. You will be responsible for developing complex PHY algorithms, system integration, and bringing up chips for BT. This position offers a unique opportunity to work on algorithm design, hardware implementation, and collaborate with cross-functional teams to ensure successful integration and deployment of Bluetooth solutions. Your key responsibilities will include Bluetooth PHY baseband algorithm development, optimizing system performance, participating in the design of High Data Transmission (HDT) and Bluetooth Higher Band (HB) IPs, silicon bring-up, and productization of existing Bluetooth IPs. You should have a solid background in communication theory and signal processing, experience in wireless communication physical layers such as Bluetooth, Wireless LAN, Thread/Zigbee, UWB, etc., and hands-on experience with chip bring-up and calibration algorithms optimization. We are looking for a proactive, self-starting individual with excellent organizational skills, a positive attitude, and strong communication skills. You should be a team player with the ability to work collaboratively within a diverse team. The ideal candidate will hold a Bachelor's degree in Communication Engineering or a related field, have at least 8 years of experience in systems engineering in modem design, and experience in modem design in wireless standards like WiFi/BT/LTE/5G. Believing in diversity, we offer a dynamic work environment where you can explore new ideas, solve complex problems, and contribute to the development of cutting-edge technology. If you are enthusiastic, adaptable, and reliable, we invite you to join our team at Synaptics.,

As an ASIC Verification Engineer at our game-changing AI solutions company, you will be responsible for developing verification environments for modules, subsystems, top level, and FPGA. You will build models, checkers, and random test frameworks using SystemVerilog and UVM. Additionally, you will participate in Low power analysis (UPF), power estimation, and C modeling. Your role will also involve performing lint, CDC, code coverage, and functional coverage, as well as formal verification of modules using SVA assertions. To excel in this role, you should have experience in verifying complex subsystems and ASICs. You should be adept at building scalable verification environments from scratch and proficient in Verilog, UVM, EDA tools, scripting, automation, build, and regression systems. Exposure to FPGA emulation platforms, silicon bringup, and board debug will be beneficial for this position. A degree in BTech/MTech in EE/CS with any level of experience is required to be considered for this opportunity. If you are passionate about pushing the boundaries of AI technology and want to be a part of the edge AI revolution, we look forward to hearing from you. Please reach out to us at +91-9071106778 to explore this exciting opportunity further.,

As a candidate for this position, you should hold a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or possess equivalent practical experience. Additionally, you should have at least 5 years of experience in High Bandwidth Memory/Double Data Rate (HBM/DDR) technology. Your responsibilities will include silicon bringup, functional validation, characterizing, and qualification, as well as working with board schematics, layout, and debug methodologies utilizing lab equipment. Preferred qualifications for this role include experience in hardware emulation with hardware/software integration, proficiency in coding languages such as Python for automation development, and experience in Register-Transfer Level (RTL) design, verification, or emulation. Knowledge of SoC architecture, boot flows, and HBM/DDR standards will be advantageous. In this role, you will contribute to shaping the future of AI/ML hardware acceleration by working on cutting-edge TPU (Tensor Processing Unit) technology that powers Google's AI/ML applications. You will be part of a team dedicated to developing custom silicon solutions for Google's TPUs, with a focus on design and verification expertise related to TPU architecture and AI/ML-driven systems. Your primary responsibility will be the post-silicon validation of Cloud Tensor Processing Unit (TPU) projects. This will involve creating test plans and content for subsystem testing, verifying content on pre-silicon platforms, executing tests on post-silicon platforms, and debugging issues. Collaboration with engineers from various teams will be essential in validating functional, power, performance, and electrical characteristics of the Cloud TPU silicon to ensure high-quality designs for next-generation data center accelerators. The ML, Systems, & Cloud AI (MSCA) organization at Google is involved in designing, implementing, and managing hardware, software, machine learning, and systems infrastructure for Google services and Google Cloud. Your work will impact millions of users worldwide by prioritizing security, efficiency, and reliability in developing TPUs and running a global network. Your responsibilities will include developing and executing tests for memory controller High Bandwidth Memory (HBM) post-silicon validation, driving debugging efforts, ensuring validation coverage, and assisting in pre-silicon integration and validation on hardware emulators.,

GlobalFoundries is currently seeking a highly motivated Memory Design Engineer to join the Memory IP group in the Global Organization, located in Bangalore. In this role, you will be responsible for developing CMOS memories such as SP SRAM, DP SRAM, Register File, and ROM. Your tasks will include circuit design, simulation, margining, and characterization of full custom circuits, as well as functional simulations and statistical analysis. You will also be involved in verifying bit cells, physical layout design and verification, and signing off and releasing the memory IPs on dedicated IP validation test chips. Additionally, you will support silicon bring-up and characterization, participate in implementation & design/layout reviews, and contribute innovative ideas for addressing design problems. Collaboration with IP design and layout teams will be a key aspect of this role. The ideal candidate should hold a Bachelors/Master's degree in Electrical (VLSI, Microelectronics, or related fields) from a reputable university with a minimum of 4-12 years of work/industry experience. Proficient knowledge and experience with EDA tools such as Cadence, Mentor Graphics, and Synopsys for schematic design & simulations are required. Experience in SRAM Memory designs, timing characterization, and Verilog is desirable. General analog mixed-signal design concepts knowledge is also preferred. Strong technical verbal and written communication skills are essential, along with the ability to work effectively with cross-functional teams. Preferred qualifications include knowledge in various technologies (Bulk, CMOS & SOI) process, hands-on experience with state-of-the-art memory or analog design flows, and programming skills applicable to design flow automation tasks. The ability to work within a dynamic interdisciplinary environment, knowledge of different technology nodes, and proficiency in communicating and working efficiently in an international multi-disciplinary setting are advantageous. Strong analytical and problem-solving skills are a must. GlobalFoundries is an equal opportunity employer that values diversity and inclusion in the workplace. We believe that a multicultural environment enhances productivity, efficiency, and innovation, while ensuring that all employees feel respected, valued, and heard. For more information about our benefits, please visit: https://gf.com/about-us/careers/opportunities-asia,

You will be working as a DFT Engineer in Noida with the following responsibilities: Strong fundamental knowledge of DFT techniques including JTAG, ATPG, yield learning, logic diagnosis, Scan compression, IJTAG, and MBIST/LBIST. Experience in Tessent based ATPG flow, GLS, and Post-silicon-debug. Proficient in Perl/Tcl/Python scripting for automation and efficiency. Demonstrate excellent analytical and problem-solving skills. Conduct Core and SOC level ATPG to ensure Automotive grade quality. Handle Hierarchical ATPG retargeting and Pattern release for application on ATE. Execute SOC and Core level Timing/Non-timing GLS. Support silicon bring-up, diagnosis, and physical failure analysis. Facilitate Emulation of Gate-level SCAN patterns for comprehensive testing. You should possess a minimum of 5 years of experience in a similar role and hold a BTECH/MTECH degree in Electrical/Electronics/Computer Science Engineering or an equivalent field.,

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 5 years of experience in High Bandwidth Memory/Double Data Rate (HBM/DDR). Experience in silicon bringup, functional validation, characterizing, and qualification. Experience with board schematics, layout, and debug methodologies with using lab equipment. Preferred qualifications: Experience in hardware emulation with hardware/software integration. Experience in coding (e.g., Python) for automation development. Experience in Register-Transfer Level (RTL) design, verification or emulation. Knowledge of SoC architecture including boot flows. Knowledge of HBM/DDR standards. Responsibilities Develop and execute tests for memory controller High Bandwidth Memory (HBM) post-silicon validation and on hardware emulators and assist in bring-up processes from prototyping through post-silicon validation. Drive debugging and investigation efforts to root-cause, cross-functional issues. This includes pre-silicon prototyping platforms as well as post-silicon bringup and production. Ensure validation provides necessary functional coverage for skilled design. Help operate and maintain our hardware emulation platform for pre-silicon integration and validation.

You should hold a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or possess equivalent practical experience. Additionally, you should have at least 5 years of experience in Application-Specific Integrated Circuit (ASIC) design for test, encompassing the silicon life cycle through DFT pattern bring-up on Automatic Test Equipment (ATE) and manufacturing. It is crucial to have familiarity with ATPG, Low Value (LV), Built-in self-test (BIST), or Joint Test Action Group (JTAG) tool and flow. Ideally, you should also have experience with a programming language like Perl, along with expertise in Synthesis, Lint, Change Data Capture (CDC), Local Enhanced Content (LEC), DFT timing, and Static Timing Analysis (STA). Proficiency in performance design DFT techniques, understanding of the end-to-end flows in Design, Verification, DFT, and Partner Domains (PD), and the ability to scale DFT would be advantageous. As part of our dynamic team, you will be involved in developing custom silicon solutions that drive the future of Google's direct-to-consumer products. Your contributions will play a pivotal role in the innovation of products that are cherished by millions globally. Your skills will influence the next wave of hardware experiences, delivering exceptional performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team synergizes the best of Google AI, Software, and Hardware to craft profoundly beneficial experiences. We are dedicated to researching, designing, and advancing new technologies and hardware to enhance computing speed, seamlessness, and power, ultimately striving to enhance people's lives through technology. Your responsibilities will include collaborating with a team dedicated to Design for Testing (DFT) verification, Pattern generation, Standard Delay Format (SDF) simulations, Static Timing Analysis (STA) checks. You will be tasked with crafting Pattern delivery using Automatic Test Pattern Generation (ATPG), engaging in Silicon bring-up, working on Yield, Vmin or Return Materials/Merchandise Authorization (RMA) debug, and delivering debug patterns while conducting Silicon data analysis.,

Minimum qualifications: You should hold a Bachelor's degree in Electrical Engineering, a related field, or possess equivalent practical experience. Additionally, you must have at least 5 years of experience in DFT specification definition architecture and insertion. A minimum of 3 years of experience using electronic design automation (EDA) test tools (e.g., Spyglass, Tessent) is required. Your background should also include experience with ASIC DFT synthesis, STA, simulation, and verification flow. It is essential to have experience collaborating with ATE engineers, involving tasks such as silicon bring-up, patterns generation, debug, validation on automatic test equipment, and resolution of silicon issues. Preferred qualifications: A Master's degree in Electrical Engineering or a related field would be advantageous. Moreover, experience in IP integration (e.g., memories, test controllers, TAP, and MBIST), SoC cycles, silicon bring-up, and silicon debug activities, as well as fault modeling, would be beneficial for this role. About the job: Join a forward-thinking team dedicated to developing custom silicon solutions that drive the future of Google's direct-to-consumer products. Your contributions will play a vital role in the innovation process behind products cherished by millions globally. As part of this role, you will be tasked with defining, implementing, and deploying advanced Design for Testing (DFT) methodologies for digital, mixed-signal chips, or IPs. Responsibilities include defining silicon test strategies, DFT architecture, creating DFT specifications for next-generation SoCs, designing, inserting, and verifying the DFT logic, and collaborating with test engineers. Your role will focus on reducing test costs, improving production quality, and enhancing yield. Responsibilities: Your responsibilities will involve developing DFT strategy and architecture, encompassing hierarchical DFT/Memory Built-In Self Test (MBIST), IJTAG/TAP, and Hi-Speed IO. You will demonstrate ownership from DFT logic development and pre-silicon verification to collaboration with test engineers post silicon. Additionally, you will insert various DFT logic components, such as boundary scan, scan chains, DFT Compression, Logic Built-In Self Test (BIST), Test Access Point (TAP) controller, and Clock Control block. Furthermore, you will be responsible for inserting and connecting MBIST logic components, documenting DFT architecture and test sequences, and ensuring compliance with Test Design Rule Checks (TDRC) to achieve high test quality and support the post-silicon test team effectively.,

As a candidate for the role, you should possess a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or have equivalent practical experience. Additionally, you need to have at least 5 years of experience in Application-Specific Integrated Circuit (ASIC) design for test, including managing the silicon life cycle through DFT pattern bring-up on Automatic Test Equipment (ATE) and manufacturing. It is crucial that you have familiarity with ATPG, Low Value (LV), Built-in Self Test (BIST), or Joint Test Action Group (JTAG) tool and flow. Preferred qualifications for this position include proficiency in a programming language such as Perl, along with experience in Synthesis, Lint, Change Data Capture (CDC), Local Enhanced Content (LEC), DFT timing, and Static Timing Analysis (STA). An understanding of performance design DFT techniques, end-to-end flows in Design, Verification, DFT, and Partner Domains (PD), as well as the ability to scale DFT will be advantageous. Joining our team means being part of a group that continually pushes boundaries, focusing on developing custom silicon solutions that drive the future of Google's direct-to-consumer products. Your contributions will play a pivotal role in the innovation that underpins products adored by millions globally. Your expertise will be instrumental in shaping the next wave of hardware experiences, delivering unmatched performance, efficiency, and integration. At Google, our mission is to organize the world's information and make it universally accessible and useful. Our collaborative team leverages the best of Google AI, Software, and Hardware to create exceptionally helpful experiences. We are dedicated to researching, designing, and developing new technologies and hardware to make computing faster, seamless, and more powerful, ultimately aiming to enhance people's lives through technology. In this role, your responsibilities will include collaborating with a team focusing on Design for testing (DFT) verification, Pattern generation, Standard Delay Format (SDF) simulations, and Static Timing Analysis (STA) checks. You will be tasked with writing a Pattern delivery using Automatic Test Pattern Generation (ATPG), contributing to Silicon bring-up, working on Yield, Vmin or Return Materials/Merchandise Authorization (RMA) debug, and delivering debug patterns, as well as performing Silicon data analysis.,

As an RTL Design Engineer at Google, you will utilize your expertise in designing RTL digital logic using System Verilog for FPGA/Application-Specific Integrated Circuit (ASIC). Your role will involve scripting in languages such as Perl or Python, as well as focusing on area, power, and performance optimization. Ideally, you hold a Master's degree or PhD in Electrical Engineering, Computer Science, or possess equivalent practical experience. Experience in designing and developing security blocks or crypto blocks will be beneficial for this position. Join a diverse team at Google that is dedicated to pushing boundaries and creating custom silicon solutions for the future of direct-to-consumer products. Your contributions will drive innovation behind globally loved products, shaping the next generation of hardware experiences with a focus on performance, efficiency, and integration. In this role, you will be responsible for Register-Transfer Level (RTL) design development of security IP and subsystems. This includes tasks such as Micro architecture, RTL coding, UPF definition, constraints, IP release flows, Power Performance Area (PPA) optimizations, test planning collaboration, coverage reviews, and closure to ensure high-quality and optimized security designs. At Google, our mission is to organize the world's information and make it universally accessible and useful. Our team combines Google AI, Software, and Hardware to create radically helpful experiences, researching, designing, and developing new technologies and hardware to enhance computing speed, seamlessness, and power for the betterment of people's lives. Your responsibilities will include participating in test planning and coverage analysis, developing RTL implementations meeting power, performance, and area goals, engaging in synthesis, timing/power closure, FPGA and silicon bring-up, Verilog/SystemVerilog RTL coding, functional and performance simulation debugging, as well as conducting Lint/CDC/FV/UPF checks. Additionally, you will create tools and scripts for task automation and progress tracking.,