Senior DFT Engineer, Google Cloud

Minimum qualifications: You should hold a Bachelor's degree in Electrical Engineering, a related field, or possess equivalent practical experience. Additionally, you must have at least 5 years of experience in DFT specification definition architecture and insertion. A minimum of 3 years of experience using electronic design automation (EDA) test tools (e.g., Spyglass, Tessent) is required. Your background should also include experience with ASIC DFT synthesis, STA, simulation, and verification flow. It is essential to have experience collaborating with ATE engineers, involving tasks such as silicon bring-up, patterns generation, debug, validation on automatic test equipment, and resolution of silicon issues. Preferred qualifications: A Master's degree in Electrical Engineering or a related field would be advantageous. Moreover, experience in IP integration (e.g., memories, test controllers, TAP, and MBIST), SoC cycles, silicon bring-up, and silicon debug activities, as well as fault modeling, would be beneficial for this role. About the job: Join a forward-thinking team dedicated to developing custom silicon solutions that drive the future of Google's direct-to-consumer products. Your contributions will play a vital role in the innovation process behind products cherished by millions globally. As part of this role, you will be tasked with defining, implementing, and deploying advanced Design for Testing (DFT) methodologies for digital, mixed-signal chips, or IPs. Responsibilities include defining silicon test strategies, DFT architecture, creating DFT specifications for next-generation SoCs, designing, inserting, and verifying the DFT logic, and collaborating with test engineers. Your role will focus on reducing test costs, improving production quality, and enhancing yield. Responsibilities: Your responsibilities will involve developing DFT strategy and architecture, encompassing hierarchical DFT/Memory Built-In Self Test (MBIST), IJTAG/TAP, and Hi-Speed IO. You will demonstrate ownership from DFT logic development and pre-silicon verification to collaboration with test engineers post silicon. Additionally, you will insert various DFT logic components, such as boundary scan, scan chains, DFT Compression, Logic Built-In Self Test (BIST), Test Access Point (TAP) controller, and Clock Control block. Furthermore, you will be responsible for inserting and connecting MBIST logic components, documenting DFT architecture and test sequences, and ensuring compliance with Test Design Rule Checks (TDRC) to achieve high test quality and support the post-silicon test team effectively.,