Senior DFT Engineer, Google Cloud Google

3.0 - 7.0 years

0 Lacs

karnataka

On-site

Minimum qualifications: You should hold a Bachelor's degree in Electrical Engineering, a related field, or possess equivalent practical experience. Additionally, you must have at least 5 years of experience in DFT specification definition architecture and insertion. A minimum of 3 years of experience using electronic design automation (EDA) test tools (e.g., Spyglass, Tessent) is required. Your background should also include experience with ASIC DFT synthesis, STA, simulation, and verification flow. It is essential to have experience collaborating with ATE engineers, involving tasks such as silicon bring-up, patterns generation, debug, validation on automatic test equipment, and resolution of silicon issues. Preferred qualifications: A Master's degree in Electrical Engineering or a related field would be advantageous. Moreover, experience in IP integration (e.g., memories, test controllers, TAP, and MBIST), SoC cycles, silicon bring-up, and silicon debug activities, as well as fault modeling, would be beneficial for this role. About the job: Join a forward-thinking team dedicated to developing custom silicon solutions that drive the future of Google's direct-to-consumer products. Your contributions will play a vital role in the innovation process behind products cherished by millions globally. As part of this role, you will be tasked with defining, implementing, and deploying advanced Design for Testing (DFT) methodologies for digital, mixed-signal chips, or IPs. Responsibilities include defining silicon test strategies, DFT architecture, creating DFT specifications for next-generation SoCs, designing, inserting, and verifying the DFT logic, and collaborating with test engineers. Your role will focus on reducing test costs, improving production quality, and enhancing yield. Responsibilities: Your responsibilities will involve developing DFT strategy and architecture, encompassing hierarchical DFT/Memory Built-In Self Test (MBIST), IJTAG/TAP, and Hi-Speed IO. You will demonstrate ownership from DFT logic development and pre-silicon verification to collaboration with test engineers post silicon. Additionally, you will insert various DFT logic components, such as boundary scan, scan chains, DFT Compression, Logic Built-In Self Test (BIST), Test Access Point (TAP) controller, and Clock Control block. Furthermore, you will be responsible for inserting and connecting MBIST logic components, documenting DFT architecture and test sequences, and ensuring compliance with Test Design Rule Checks (TDRC) to achieve high test quality and support the post-silicon test team effectively.,

Posted 2 weeks ago

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VLSI MBIST Engineer Coventine Digital

4.0 - 8.0 years

5 - 15 Lacs

Bengaluru

Work from Office

Job Description : We are looking for a VLSI MBIST Engineer with strong expertise in Memory Built-In Self-Test (MBIST) methodologies for ASIC/SoC designs. The ideal candidate should have hands-on experience using Synopsys SMS tool and a solid understanding of MBIST test development, pattern generation, and fault simulation. Key Responsibilities : Develop and implement MBIST algorithms and test patterns for embedded memories (SRAM, DRAM, ROM, CAM) Use Synopsys SMS tool for MBIST pattern generation and validation Perform fault modeling, fault simulation, and fault coverage analysis Integrate MBIST macros into SoC designs in collaboration with RTL and physical design teams Debug MBIST issues in pre- and post-silicon stages Document MBIST flows, generate test reports, and provide support for DFT reviews Stay updated on industry trends and best practices in MBIST and memory testing Required Skills : B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, VLSI, or related fields 4+ years of experience in MBIST implementation and validation Strong experience with Synopsys SMS tool Proficiency in scripting languages like TCL, Perl, or Python Good knowledge of Verilog/SystemVerilog and digital design fundamentals Familiarity with simulation tools like VCS, ModelSim Preferred Skills : Experience with DFT tools such as Tessent Knowledge of ATPG, JTAG (IEEE 1149.1), and IEEE 1500 standards Exposure to silicon bring-up and failure analysis

Posted 3 weeks ago

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Structural Geologist ( Reservoir Characterization) Consult Asia

10.0 - 15.0 years

35 - 50 Lacs

Bengaluru

Work from Office

Deliver structural interpretation and fault framework modeling to evaluate reservoir trap geometry, seal integrity, and compartmentalization using seismic and wellbore data Required Candidate profile Geoscientists with strong skills in seismic interpretation, fault modeling, and structural analysis. Ability to contribute to exploration, basin modeling, and field development projects

Posted 2 months ago

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