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7 Ijtag Jobs

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3.0 - 5.0 years

15 - 20 Lacs

bengaluru

Work from Office

3-5 Years experience in DFT Experience with IJTAG is a must. Hands-on experience in scan insertion, ATPG DRC, and coverage analysis Please do share your updated resume to - dft@greensemis.com Accessible workspace Flexi working Health insurance

Posted 8 hours ago

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8.0 - 10.0 years

0 Lacs

bengaluru, karnataka, india

On-site

Job Description Arms Solutions group DFT team implements DFT for test-chips and hard-macros to prove Arm&aposs soft IP power, performance, area, and functionality within the context of a SoC using the latest DFT techniques and process technologies. We closely collaborate with RTL, Verification, Physical Implementation, and Test engineering teams throughout the life cycle of a project, from an early investigation stage all the way through tape-out and silicon test/characterization on ATE. Responsibilities Architect, Implement, and validate innovative DFT techniques on test-chips and hard-macros. Insert DFT logic into SoC-style designs at the RTL level and at the Synthesis gate level, validate...

Posted 1 week ago

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4.0 - 8.0 years

0 Lacs

karnataka

On-site

You should have a minimum of 4 years of experience in the field. You must be proficient in using Synthesis and netlist validation tools, particularly LEC and Spyglass checks, as well as scan insertion and DRC debug. It is essential to be well-versed in both Synopsys and Mentor Graphics DFT flows. Your expertise should also include experience in Scan Compression for Hierarchical and Modular EDT, ATPG, and Coverage debug, along with the ability to manage multiple clock domains and familiarity with the OCC flow. You should have practical experience in BIST and BISR insertion and Validation with SMS and MBIST Architect. Hands-on experience with JTAG, IJTAG, and SSN is required. You should be fam...

Posted 2 weeks ago

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5.0 - 9.0 years

0 Lacs

noida, uttar pradesh

On-site

You will be working as a DFT Engineer in Noida with the following responsibilities: Strong fundamental knowledge of DFT techniques including JTAG, ATPG, yield learning, logic diagnosis, Scan compression, IJTAG, and MBIST/LBIST. Experience in Tessent based ATPG flow, GLS, and Post-silicon-debug. Proficient in Perl/Tcl/Python scripting for automation and efficiency. Demonstrate excellent analytical and problem-solving skills. Conduct Core and SOC level ATPG to ensure Automotive grade quality. Handle Hierarchical ATPG retargeting and Pattern release for application on ATE. Execute SOC and Core level Timing/Non-timing GLS. Support silicon bring-up, diagnosis, and physical failure analysis. Facil...

Posted 1 month ago

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12.0 - 22.0 years

40 - 85 Lacs

Bengaluru

Hybrid

Location :- Bangalore Experience :- 12-20 years Required Skills And Experience: This role is for a Principal DFT engineer with 15 years plus experience Technical leadership in DFT and ability to train/work with junior team members Experience with Perl, TCL, and/or python with ability to build and deploy generic DFT flows Proficient in Unix/Linux environments One or more core DFT skills are considered crucial for this position including some of the following Knowledge of at-speed testing, test insertion and test coverage assessment, test pattern development, scan compression, Memory BIST, Logic BIST, JTAG, IJTAG, fault simulation, debug, verification, SSN, designing and conducting experiments...

Posted 1 month ago

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5.0 - 9.0 years

0 Lacs

Bengaluru / Bangalore, Karnataka, India

On-site

Introduction As a Hardware Developer at IBM, youll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable IBM customers to make better decisions quicker on the most trusted hardware platform in todays market. Your Role and Responsibilities : We are seeking highly motivated DFT engineer to be part of Hardware team. Join a great team of engineering professionals who are involved in development, validation, and delivery of DFT patterns for IBMs microprocessor chip design team. As a member of functional DFT team ( Power on Reset, Architecture Verification Program, Array BIST teams ), you will be required but n...

Posted 3 months ago

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3.0 - 8.0 years

6 - 16 Lacs

noida, bengaluru

Work from Office

Block & Soc level DFT insertion. Scan insertion & DRC cleanup. ATPG, Pattern generation for Stuck-At, at-speed test, iddq, path delay, fault grading. Coverage debug. Memory testing, MBIST Pattern generation.

Posted Date not available

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