516 Systemverilog Jobs - Page 8

Description We are seeking a skilled Verification Engineer to join our team in India. The ideal candidate will have a strong background in digital design verification and will be responsible for ensuring the quality and reliability of our products through rigorous testing and analysis. Responsibilities Develop and implement verification plans and test cases for digital designs. Perform functional and performance verification using simulation and formal verification techniques. Collaborate with design engineers to understand specifications and requirements. Debug and analyze issues found during verification, providing feedback to design teams. Generate reports and documentation for verification activities and results. Skills and Qualifications 3-6 years of experience in GLS verification engineering or related field. Strong knowledge of digital design concepts and verification methodologies. Proficiency in SystemVerilog and UVM (Universal Verification Methodology). Experience with simulation tools like ModelSim, Questa, or similar. Familiarity with scripting languages such as Perl, Python, or TCL for automation tasks. Understanding of RTL design and coding practices. Ability to work collaboratively in a team environment and communicate effectively.

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. Position: DV Engineer -GLS Location: Bangalore Work Type: Onsite Job Type: Full time Job Description: Key Responsibilities: Develop and implement scalable UVM-based verification environments Lead and execute GLS (Gate-Level Simulation)timing-aware and glitch-sensitive validation is a core part of this role Perform Clock Domain Crossing (CDC) verification using industry-standard methodologies Collaborate cross-functionally with RTL, DFT, and system teams for end-to-end verification closure Analyze waveforms, root-cause issues, and contribute to debugging complex logic Requirements: Required Skills: Solid hands-on experience with SystemVerilog and UVM methodologies Strong understanding and application of GLS (Gate-Level Simulation) techniques Experience with CDC verification and asynchronous domain handling Familiarity with tools such as VCS, Questa, Incisive Scripting knowledge (Python, Perl, or Shell) is a plus TekWissen Group is an equal opportunity employer supporting workforce diversity.

We’re Hiring – SoC & GLS Verification Engineers! 📍 Location: Bangalore / Hyderabad 🧠 Experience: 5–10 Years Join our growing team at BITSILICA and work on cutting-edge SoC designs! 🔧 Skills We’re Looking For: ✔️ SoC & GLS Verification ✔️ SystemVerilog, UVM, C ✔️ AMBA protocols (AXI, AHB, APB) ✔️ DSP module verification (Nice to have) 📩 Send your resume to: Viswanadha.reddy@bitsilica.com

Job Title: Lead FPGA Design Engineer Experience Required: 6+ years Location: Hyderabad/Bangalore Job Type: Full-time Industry: Semiconductor / Electronics / Embedded Systems Job Summary: We are looking for a highly skilled and experienced Lead FPGA Design Engineer to join our hardware design team. The ideal candidate will lead the design, implementation, verification, and validation of FPGA-based systems for complex hardware products. This role involves mentoring junior engineers, collaborating with cross-functional teams, and ensuring delivery of high-performance, high-reliability designs. Key Responsibilities: Lead architecture definition and design of complex FPGA solutions using VHDL/Verilog/SystemVerilog. Translate system-level requirements into FPGA design specifications. Hands-on implementation of FPGA designs using Xilinx, Intel (Altera), or Lattice FPGAs. Develop testbenches and perform simulation using tools like ModelSim, Questa, or VCS. Integrate and validate FPGA designs on hardware, working closely with board design and software teams. Use industry-standard tools such as Vivado, Quartus, Synplify, etc. Lead FPGA timing closure, floor planning, and resource optimization. Perform version control, documentation, and design reviews. Guide and mentor a team of junior engineers; ensure design best practices and quality processes are followed. Required Skills and Experience: Bachelor’s or Master’s degree in Electronics/Electrical/Computer Engineering. 6+ years of industry experience in FPGA design and verification. Expertise in VHDL/Verilog/SystemVerilog coding and simulation. Experience with FPGA toolchains such as Xilinx Vivado, Intel Quartus, Synplify. Strong knowledge of high-speed interfaces (e.g., PCIe, DDR, Ethernet, AXI). Familiar with embedded processor systems (MicroBlaze, Nios II, ARM SoCs). Proficiency in scripting (Tcl, Python, Shell) for automation. Experience with static timing analysis, constraints definition (SDC), and debugging. Good understanding of hardware/software integration. Excellent leadership, problem-solving, and communication skills. Preferred Qualifications: Prior experience in leading FPGA teams or projects. Exposure to safety-critical or mission-critical design environments (e.g., automotive, aerospace, medical). Experience with hardware emulation or ASIC prototyping on FPGAs. Familiarity with version control systems (Git, SVN) and documentation tools. Why Join Us? Work on cutting-edge FPGA designs in a collaborative environment. Competitive compensation with leadership opportunities. Growth-focused, innovation-driven engineering culture. Interested can share CV to sharmila.b@acldigital.com

Principal Design Verification Engineer (India) Bangalore (Hybrid ) / Hyderabad (Hybrid ) Principal Design Verification Engineer (India) India Company Background Introducing The Information’s 50 Most Promising Startups for 2024 We areon a mission to revolutionize AI compute systems and infrastructure at scale through the development of superior-scaling networking silicon and software which we call the Accelerated Compute Fabric. Founded and led by an executive team assembled from first-class semiconductor and distributed systems/software companies throughout the industry, sets themselves apart from other startups with a very strong engineering pedigree, a proven track record of delivering, deploying and scaling products in data center production environments, and significant investor support for our ambitious journey! Together, with their differentiated approach to solving the I/O bottlenecks in distributed AI and accelerated compute clusters, We are unleashing the revolution in next-gen computing fabrics. Summary Join an ambitious, experienced team of silicon and distributed systems experts as a design verification engineer. You have the opportunity to build a groundbreaking new category of product that revolutionizes the performance and scalability of next-generation distributed computing systems, and to help solve key infrastructure challenges facing our customers. We are looking for talented, motivated candidates with experience designing and verifying large-scale networking and computing chips, and who are looking to grow in a fast paced, dynamic startup environment. We seek experienced verification engineers who can contribute across the full lifecycle of complex chip development, from microarchitecture definition to DV infrastructure and test development, to post-silicon testing. Roles and Responsibilities Collaborate with world-class distributed systems hardware and software architects to transform product vision and behavioral specifications into efficient, comprehensive block-level and top-level tests which achieve outstanding coverage. Incorporate state-of-the art verification techniques to efficiently tackle the demanding scale and performance requirements of a functionally complex device. Define and implement infrastructure for effective HW/SW co-simulation. Execute on a verification strategy which ensures that the prototype meets both the device level specifications as well as the system-level requirements. The ideal candidate should have the versatility to build infrastructure and tests that can be leveraged across both ASIC and FPGA platforms. Skills/Qualifications Proven industry experience and successful track record in verifying chip- and block-level RTL designs for high-performance networking or computing chips, such as Network Interface Controllers, Smart-NICs, DPUs, accelerators, and/or switches in advanced silicon geometries. DDR5 Deep experience with full chip verification and infrastructure development. Strong current knowledge of UVM constructs, components, and practices. Expert knowledge of SystemVerilog, as well as Python or other scripting languages. Experience with C/C++ and general software engineering principles is highly desirable. Minimum BSEE/CE + 12-20years or MSEE/CE + 10-18 years experience. Proven track record of design execution and quality on products which have shipped in high-volume. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Principal Physical Design Engineer Greater Bangalore -Hybrid/Hyderabad (Hybrid ) PrincipalPhysical Design Engineer Company Background We are a well-funded, stealth-mode startup based in Mountain View, CA, founded by senior technical and business executives hailing from category leaders in infrastructure semiconductors and hyperscale cloud services, and backed by top-tier investors with an immensely successful formula & track record on early-stage investments. We are a diverse team of expert chip/software/systems architects and developers who excel in hardware/software solution co-design. Our team has built, and delivered into production, technologies that process over half of the world's global data center traffic. Summary Join an ambitious and highly experienced team of silicon and hyperscale data center systems experts as a Physical Design Engineer. Our team is motivated by a singular mission: to revolutionize the performance and scalability of next-generation distributed computing infrastructure. You have the opportunity to build a groundbreaking new category of product, working alongside some of the industry's most talented hardware and software engineers to create truly disruptive infrastructure solutions that delight our customers. We are looking for talented, motivated engineers with experience in physically implementing large-scale networking and computing semiconductor products, and who are looking to grow in a fast paced, dynamic startup environment. We are looking for experienced physical design engineers who have the range to contribute across the full lifecycle of complex chip development, from CAD tool flow setup, early floorplan exploration in conjunction with microarchitecture development, through block partitioning, power planning, clock network design and construction, through P+R, timing closure, package design, PI/SI analysis, physical verification, and tapeout. Roles and Responsibilities Build and support the CAD tool flow for physical implementation in a cloud-first development environment. Work with architects and microarchitects on the chip-level floorplan and block partitioning. Evaluate tradeoffs in functional partitioning, block size, and interface complexity with other stakeholders. Define and construct the major physical structures, including the clock and reset architecture, the power delivery network, and interconnect topologies. Execute on block-level, cluster-level, and top-level physical implementation, from synthesis, floorplan and power plan, through P+R, through timing closure, physical verification, and tapeout. Interface with foundry and library partners on 3rd party IP and process technology issues, including updates to device models, IP integration requirements, and pre-tapeout signoff. Skills/Qualifications : Proven industry experience and successful track record in the physical implementation of large, high-performance network switching/routing fabrics (Ethernet, Infiniband, HPC), Network Interface Controllers, Smart-NICs, CPUs, or GPUs in the latest silicon process nodes. Deep experience with the latest CAD tools through the entire physical design workflow, e.g., Cadence Genus and Innovus, Synopsys ICC2/FusionCompiler, Tempus, PrimeTime SI, PrimeTime PX, StarRC, ICV, Calibre. Strong familiarity with various analysis tools such as Redhawk, Voltus. Experience with circuit analysis using HSPICE is a plus. Expert knowledge of SystemVerilog, as well as Perl, Python or other scripting languages. Minimum BSEE/CE + 12 years or MSEE/CE + 10 years experience. Proven track record of execution on products which have shipped in high-volume. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Principal Physical Design Engineer Greater Bangalore -Hybrid/Hyderabad (Hybrid ) PrincipalPhysical Design Engineer Company Background We are a well-funded, stealth-mode startup based in Mountain View, CA, founded by senior technical and business executives hailing from category leaders in infrastructure semiconductors and hyperscale cloud services, and backed by top-tier investors with an immensely successful formula & track record on early-stage investments. We are a diverse team of expert chip/software/systems architects and developers who excel in hardware/software solution co-design. Our team has built, and delivered into production, technologies that process over half of the world's global data center traffic. Summary Join an ambitious and highly experienced team of silicon and hyperscale data center systems experts as a Physical Design Engineer. Our team is motivated by a singular mission: to revolutionize the performance and scalability of next-generation distributed computing infrastructure. You have the opportunity to build a groundbreaking new category of product, working alongside some of the industry's most talented hardware and software engineers to create truly disruptive infrastructure solutions that delight our customers. We are looking for talented, motivated engineers with experience in physically implementing large-scale networking and computing semiconductor products, and who are looking to grow in a fast paced, dynamic startup environment. We are looking for experienced physical design engineers who have the range to contribute across the full lifecycle of complex chip development, from CAD tool flow setup, early floorplan exploration in conjunction with microarchitecture development, through block partitioning, power planning, clock network design and construction, through P+R, timing closure, package design, PI/SI analysis, physical verification, and tapeout. Roles and Responsibilities Build and support the CAD tool flow for physical implementation in a cloud-first development environment. Work with architects and microarchitects on the chip-level floorplan and block partitioning. Evaluate tradeoffs in functional partitioning, block size, and interface complexity with other stakeholders. Define and construct the major physical structures, including the clock and reset architecture, the power delivery network, and interconnect topologies. Execute on block-level, cluster-level, and top-level physical implementation, from synthesis, floorplan and power plan, through P+R, through timing closure, physical verification, and tapeout. Interface with foundry and library partners on 3rd party IP and process technology issues, including updates to device models, IP integration requirements, and pre-tapeout signoff. Skills/Qualifications : Proven industry experience and successful track record in the physical implementation of large, high-performance network switching/routing fabrics (Ethernet, Infiniband, HPC), Network Interface Controllers, Smart-NICs, CPUs, or GPUs in the latest silicon process nodes. Deep experience with the latest CAD tools through the entire physical design workflow, e.g., Cadence Genus and Innovus, Synopsys ICC2/FusionCompiler, Tempus, PrimeTime SI, PrimeTime PX, StarRC, ICV, Calibre. Strong familiarity with various analysis tools such as Redhawk, Voltus. Experience with circuit analysis using HSPICE is a plus. Expert knowledge of SystemVerilog, as well as Perl, Python or other scripting languages. Minimum BSEE/CE + 12years or MSEE/CE + 10 years experience. Proven track record of execution on products which have shipped in high-volume. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

IPrincipal P/RTL Design Engineer for ARM CMN Fabric and Neoverse Hyderabad / Bangalore Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore Principal IP/RTL Design Engineer for ARM CMN Fabric and Neoverse Position Overview Seeking an IP/RTL Design Engineer with 10+ years of experience to design IP/RTL for ARM Neoverse-based SoCs, focusing on CMN fabric, using Socrates for configuration, targeting AI/HPC datacenter applications. Key Responsibilities Design IP blocks for ARM Neoverse SoCs, integrating CMN fabric (e.g., CMN-700/S3) for cache coherence and interconnect. Develop Verilog/SystemVerilog RTL for high-performance, low-latency designs. Configure CMN topologies using Arm Socrates for optimized performance and scalability. Implement protocols like AMBA CHI, ACE, CXL, PCIe for coherent interconnects. Optimize designs for bandwidth, latency, and power in AI/HPC workloads. Support synthesis, timing closure, and FPGA prototyping and Design Verification team Document microarchitecture and design specifications. Required Qualifications Education: BS/MS/PhD in Electronics/Computer Engineering. Experience: 10+ years in ASIC/FPGA IP/RTL design, 5+ years with ARM Neoverse and CMN fabrics (e.g., CMN-600/700/S3). Skills: Expert in Verilog/SystemVerilog RTL design. Deep knowledge of ARM Neoverse (V1/V3/N2/N3) and CMN interconnects. Deep understanding in system architecture, coherence and cache Experience with Arm Socrates for CMN configuration. Proficiency in AMBA CHI, CXL, PCIe, or CCIX protocols. Familiarity with synthesis and timing tools (e.g., Synopsys Design Compiler). Experience with AI/HPC or datacenter SoC design. Knowledge of DDR5, HBM3, or chiplet-based architectures. Familiarity with UALink or Ultra Ethernet. Strong problem-solving and collaboration skills. What is in it for you? Pure play product work environment Chance to work with a tightly knit group of exceptional engineers who come from the top companies of the Semiconductor world Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. A meritocracy first work place where each peer is a star A chance to be a part of industry shaping product in entirety (not bits and pieces) from initial stages A chance to work at a startup which already has customers and investor lined up for their product pipeline (We do not have a marketing/sales team, because we do not need them). A chance to learn from industry veterans who have already launched multiple Billion Dollar Semiconductor firms over the last 3 decades. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Principal IP/RTL Design Engineer for TPU Hyderabad / Bangalore Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore IP/RTL Design Engineer for TPU Position Overview Seeking an IP/RTL Design Engineer with 5+ years of experience to design IP/RTL for TPUs, focusing on high-performance matrix multiplication, low-latency interconnects, and power-efficient AI acceleration. Key Responsibilities Design IP blocks for TPU cores, including systolic arrays, vector units, and memory subsystems. Develop Verilog/SystemVerilog RTL for performance, timing, and area optimization. Implement high-speed interconnects (e.g., AXI, NoC) for TPU data pipelines. Optimize designs for high throughput, low latency, and power efficiency in AI workloads. Integrate LPDDR6, HBM3, DDR5, or chiplet-based memory interfaces. Support synthesis, timing closure, and FPGA prototyping and Design Verification team Document microarchitecture and design specifications. Required Qualifications Education: BS/MS in Electrical/Computer Engineering. Experience: 10+ years in ASIC/FPGA IP/RTL design, with 3+ years in AI accelerators or TPU-like architectures. Skills: Proficient in Verilog/SystemVerilog RTL design. Knowledge of TPU architectures, systolic arrays, or matrix multiplication units. Experience with AXI, NoC, or similar interconnect protocols. Familiarity with LPDDR6, HBM3, DDR5, or high-bandwidth memory interfaces. Proficiency with synthesis and timing tools (e.g., Synopsys Design Compiler). Strong problem-solving and teamwork skills. Preferred Qualifications Experience with AI/ML workloads or datacenter TPU designs and GPU architectures Knowledge of CXL, PCIe, UALink, or Ultra Ethernet. Familiarity with power optimization for high-performance chips. What is in it for you? Pure play product work environment Chance to work with a tightly knit group of exceptional engineers who come from the top companies of the Semiconductor world Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. A meritocracy first work place where each peer is a star A chance to be a part of industry shaping product in entirety (not bits and pieces) from initial stages A chance to work at a startup which already has customers and investor lined up for their product pipeline (We do not have a marketing/sales team, because we do not need them). A chance to learn from industry veterans who have already launched multiple Billion Dollar Semiconductor firms over the last 3 decades. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Principal IP/RTL Design Engineer for Ethernet Switch Hyderabad / Bangalore Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore Position Overview IP/RTL Design Engineer for Ethernet Switch Position Overview We are seeking an experienced IP/RTL Design Engineer with over 10 years of experience to join our team in designing and developing intellectual property (IP) and RTL for Ethernet switches tailored for AI datacenter backend networks. The ideal candidate will have a strong background in digital design, ASIC/FPGA development, Ethernet protocols, and experience with high-performance interconnect protocols such as InfiniBand, NVLink, Infinity Fabric, with a focus on delivering high-performance, low-latency solutions for large-scale AI workloads. Key Responsibilities Design and optimize IP blocks (MAC, PCS, packet processors) for Ethernet switches. Develop synthesizable RTL (Verilog/SystemVerilog) meeting performance and timing goals. Optimize designs for low latency, high throughput, and power efficiency. Implement Ethernet protocols (IEEE 802.3, 100G/400G/800G), ECMP, and congestion control. Apply knowledge of InfiniBand, NVLink, or similar protocols for feature implementation. Use P4 or related languages for programmable packet processing. Collaborate with teams for synthesis, timing closure, and IP integration. Document designs and stay updated on AI networking trends. Required Qualifications Education: BS/MS/PhD in Electrical or Computer Engineering. Technical Skills: Proficient in Verilog/SystemVerilog for design. Knowledge of Ethernet (IEEE 802.3, 100G/400G/800G), ECMP, and congestion control. Experience with InfiniBand, NVLink, or similar protocols. Proficiency in P4 or programmable data plane languages. Knowledge of UALink, Ultra Ethernet, or RDMA/RoCE. Familiarity with power optimization or SDN. Familiarity with synthesis (e.g., Synopsys Design Compiler) and timing tools. Soft Skills: Strong problem-solving, communication, and teamwork skills. What is in it for you? Pure play product work environment Chance to work with a tightly knit group of exceptional engineers who come from the top companies of the Semiconductor world Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. A meritocracy first work place where each peer is a star A chance to be a part of industry shaping product in entirety (not bits and pieces) from initial stages A chance to work at a startup which already has customers and investor lined up for their product pipeline (We do not have a marketing/sales team, because we do not need them). A chance to learn from industry veterans who have already launched multiple Billion Dollar Semiconductor firms over the last 3 decades. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Job Title: Formal Verification Engineer Location: Bangalore Experience: 4+Years Job Type: Full-time Industry: Semiconductor / ASIC Design / EDA Education: B.E./B.Tech or M.E./M.Tech in ECE/EEE/Computer Engineering Job Description: We are looking for a highly motivated Formal Verification Engineer to join our Design Verification team. The candidate will be responsible for developing and executing formal verification strategies to ensure functional correctness of complex IP and SoC designs. Key Responsibilities: Define and implement formal verification strategies and plans. Develop formal properties and assertions for critical design blocks. Apply formal techniques such as property checking, sequential equivalence checking , and formal coverage. Analyze formal results, identify unreachable or vacuous properties, and refine models. Collaborate closely with RTL designers, DV engineers, and architects. Integrate formal into overall verification methodology and sign-off. Document and present formal verification methodologies, assumptions, and results. Required Skills: 4+ years of experience in formal verification using industry tools (e.g., JasperGold, VC Formal, Questa Formal, OneSpin). Strong knowledge of SystemVerilog Assertions (SVA) and formal property specification. Solid understanding of digital design concepts and RTL coding in Verilog/SystemVerilog. Familiar with formal coverage metrics and convergence techniques. Experience in debugging complex design bugs using formal tools. Ability to abstract and model designs or protocols at different levels. Desirable Skills: Familiarity with safety-critical designs (ISO 26262, DO-254) is a plus. Knowledge of common protocols: AXI, AHB, PCIe, Ethernet, etc. Exposure to sequential equivalence checking and abstraction modeling. Understanding of simulation-based verification and integration with formal. Proficiency in scripting (Python, Perl, or TCL) for automation. Interested can Share CV to sharmila.b@acldigital.com

Job Title: Design Verification Lead Location: Bangalore/Hyderabad Experience: 7+yrs Job Type: Full-time Industry: Semiconductors / VLSI / EDA Education: B.E./B.Tech or M.E./M.Tech in ECE/EEE or related field Job Description: We are looking for a passionate and experienced Design Verification Lead to drive the verification of complex SoC/IP designs. The ideal candidate will have deep expertise in functional verification methodologies and will be responsible for managing a team, defining verification strategies, and ensuring high-quality silicon delivery. Key Responsibilities: Own and lead verification activities for IP or SoC-level designs. Define and execute the verification plan, test strategy, and coverage goals. Develop and manage verification infrastructure (testbenches, stimulus, checkers, etc.). Collaborate with RTL design, DFT, PD, and firmware teams. Mentor and lead a team of verification engineers. Perform reviews of testbenches, test cases, and coverage reports. Drive simulation-based verification using SystemVerilog, UVM. Track and report project progress and debug issues independently. Participate in regression setup and continuous integration for verification. Deliver high-quality verified RTL to meet tape-out schedules. Required Skills: 7+ years of experience in ASIC/FPGA verification. Strong expertise in SystemVerilog and UVM . Hands-on experience in developing complex verification environments. Good understanding of coverage-driven verification (functional and code) . Experience with scripting languages (Perl/Python/Tcl). Knowledge of protocols like AXI, AHB, PCIe, USB, DDR, etc. Familiarity with formal verification is a plus. Strong debugging skills using waveform tools like DVE, VCS, or ModelSim. Prior experience in leading teams and driving project deliverables. Good to Have: Experience in Emulation/FPGA prototyping. Exposure to low-power verification (UPF). Knowledge of verification IPs and reuse methodologies. Hands-on with gate-level simulations and performance verification. Soft Skills: Excellent communication and interpersonal skills. Ability to lead and mentor junior engineers. Strong problem-solving and analytical thinking. Ability to work in cross-functional and global teams. Interested can share CV to sharmila.b@acldigital.com

Job Title: Design Verification Engineer Exp Level:4+yrs Location: Bangalore/Hyderabad Job Description: Responsible for ensuring functional correctness of ASIC/SoC designs. Key Task: Develop and execute verification plans for complex digital designs. Methodology: Use UVM/SystemVerilog to create testbenches, write test cases, and debug failures. Coverage: Achieve functional and code coverage targets through constrained random and directed testing. Collaboration: Work with RTL designers to identify and resolve design bugs. Tools: Leverage industry-standard tools (VCS, Questa, Verdi) for simulation and debug. Protocols: Verify IP/SoC-level designs for common protocols (AXI, APB, PCIe, DDR, etc.). Automation: Develop scripts (Python/Perl/TCL) to improve verification efficiency. Documentation: Maintain verification reports and review results with stakeholders. Compliance: Ensure adherence to project timelines and quality standards. Interested can share CV to sharmila.b@acldigital.com

Job Title: Functional Verification Engineer Location: Bangalore Experience: 4+ Years Job Type: Full-time Industry: Semiconductor / VLSI / ASIC Design Education: B.E./B.Tech or M.E./M.Tech in ECE/EEE/Computer Engineering Job Description: We are seeking a skilled and detail-oriented Functional Verification Engineer to be part of our IP/SoC verification team. The candidate will be responsible for verifying complex digital designs using industry-standard methodologies to ensure functional correctness and high-quality silicon delivery. Key Responsibilities: Develop and execute verification test plans based on design specifications and architecture. Design and implement testbenches using SystemVerilog and UVM methodology. Create constrained-random and directed test cases. Build verification components (agents, monitors, scoreboards, checkers). Perform coverage analysis (code and functional) and close coverage gaps. Debug simulation failures and work closely with design and architecture teams. Conduct regressions and analyze results for functional and performance issues. Document test plans, verification environments, and test results. Participate in design and verification reviews. Required Skills: 4+ years of hands-on experience in functional verification of IP/SoC. Strong knowledge and working experience with SystemVerilog and UVM . Familiarity with RTL design (Verilog/VHDL). Experience in coverage-driven verification, assertions, and functional coverage closure. Proficient in using simulators like VCS, Questa, or Incisive. Good scripting skills in Perl, Python, or Shell for automation. Strong debugging skills using simulation waveform viewers. Good understanding of common protocols such as AXI, AHB, APB, PCIe, USB, etc Interested can Share CV to sharmila.b@acldigital.com

Hi, Greetings from ACL Digital, Looking for CPU Verification Engineers Exp level: 4+years Location: Banglore Job Description: We are seeking a skilled and motivated CPU Verification Engineer to join our microprocessor verification team. In this role, you will contribute to the verification of high-performance, low-power CPU cores by developing scalable testbenches, driving complex test scenarios, and ensuring full functional coverage and quality sign-off Responsibilities: 1.Verification engineer with a knowledge of SoC integration verification, SoC scenario verification, SoC performance verification, CHI/DDRx/LPDDRx/AI accelarator integration verification in SoC RTL. 2.Your key responsibilities will include writing test plans, defining test methodologies, developing C based software tests, SystemVerilog/Verilog testbenches and tests, and debugging of test failures and issues. 3.Working with project management and leads on planning tasks, schedules, and reporting progress 4.Collaborate with engineers from other teams including architecture, design, implementation, modelling, performance analysis, silicon validation, FPGA and board development Required Skills and Experience : Proven understanding of digital hardware verification language Verilog/Systemverilog HDL Experience in SoC verification using Embedded Low-level programming including C/C++ tests and assembly language(preferably ARM) Experienced in one or more of various verification methodologies – UVM/OVM, formal, power aware verification, emulation Exposure to all stages of verification: requirements collection, creation of verification methodology plans, test plans, testbench implementation, test case development, documentation, and support Good Problem Solving and Debugging skills. Knowledge of SoC Verification Flow and strategy. Experience with ARM-based designs and/or ARM System Architectures, SoC Boot flow, Cache coherency Porting peripheral driver software for SoC tests Clock Domain Crossing verification Experienced in GLS, DFT/DFD, Experienced in UPF Power Aware verification Automation experience with shell programming/scripting (g. Tcl, Perl, Python etc.) Qualifications: B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, or Computer Engineering 4+ years of relevant experience in CPU or SoC-level functional verification Interested can CV to sharmila.b@acldigital.com

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. This position involves System Verilog real number modeling and functional verification of blocks involved in WAN, GPS radios for 5G products. Roles and responsibilities include: Understanding device functionality, building verification plan, functional Modeling of analog blocks in System Verilog, running and debugging testcases on a large mixed-signal SOC on RTL and Gate Level Netlists. Setting up and running AMS testbenches for RFIC modules. Working with SPICE/Spectre simulators and digital simulators (co-simulation). Analysis and debug Analog circuits. UVM/SV based Testbench creation, verification, creating self-checking tests, regression, debug, coverage analysis, bug tracking Scripting using PERL/Python/Shell to automate day to day verification tasks Working with Analog and Digital design environments like Cadence ncsim, simvision, virtuoso. Working in a fast paced environment with Analog, Digital design/DV, DFT engineers to ensure complete SoC verification Post silicon bringup support Minimum Qualifications Bachelor's degree in Electrical Engineering or Computer Engineering or related field, Masters preferred 2+ years ASIC design, verification, or related work experience Preferred Skills Experience in the following skills: Electrical circuit analysis Verilog, SystemVerilog, UVM Perl or Python Phaselock loops, ADCs, DACs, and serial programming interfaces Writing behavioral models of analog blocks including event driven simulator Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Bangalore, India • Full Time Meta Infrastructure Hardware The Infra Silicon team at Meta is responsible for designing and building in-house hardware accelerator Application-Specific Integrated Circuits (ASICs) to enhance Meta's computing efforts with capacity and efficiency at lower power and cost. The team focuses on creating domain-specific System on Chips (SoCs) that enable Meta's data centers to execute computationally-intensive workloads, such as video transcoding and AI/ML, with higher performance and lower energy consumption. They are organized into several key areas, including architecture & algorithms, design & micro-architecture, design verification, implementation & backend design, emulation/prototyping, and system on chip (SoC), which collaborate extensively with other teams to deliver comprehensive solutions for various technical domains. ASIC Engineer, Implementation Responsibilities Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power. Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them Perform Power Estimation at RTL and Gate Level and identify power reduction opportunities Run Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic Equivalency failures Perform RTL Lint and work with the Designers to create waivers Perform RTL DFT Analysis and improve the DFT coverage for Stuck-at faults Perform Flat and Hierarchical Clock Domain Crossing and work with the designers to analyze the complex clock domain crossings and sign off the CDC Perform Flat and Hierarchical Reset Domain crossing Checks. Understand the Reset-Architecture by working with Design and FW teams and develop reset groups and the corresponding reset sequence for RDC Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top-level including SOC. Analyze the inter-block timing and come up with IO budgets for the various partition blocks Develop Power Intent Specification in UPF for the multi-Vdd designs Developing Automation scripts and Methodology for all FE-tools including (Lint, CDC, RDC, Synthesis, STA, Power) Work closely with the Design Engineers, DV Engineers, Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback Minimum Qualifications Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 2+ years of experience in Design Integration and Front-End Implementation Experience with Register-Transfer Level (RTL) Synthesis and design optimization for Power, Performance, Area Knowledge of front-end and back-end ASIC tools. Experience with RTL design using SystemVerilog or other Hardware Description Language (HDL) Experience managing multiple design releases and working with cross functional teams to support and debug timing, area, power issues Experience with Electronic Design Automation (EDA) tools and scripting languages (Python, TCL) used to build tools and flows for complex environments. Experience with communicating across functional internal teams and vendors Preferred Qualifications Knowledge of Clock Domain Crossing, Reset Domain Crossing, Logic Error Correction (LEC) Synthesis Background, Timing Constraints Development, Floorplanning and Static Timing Analysis (STA) Experience Knowledge of Register-Transfer Level (RTL) coding using Verilog/System Verilog. Knowledge of Timing/physical libraries, Static Random Access Memory (SRAM) Experience with Power, Performance, Area Analysis and techniques for reducing power Knowledge of Low power design. Experience with Design Compiler, Spyglass, PrimeTime, Formality or equivalent tools Scripting and programming experience using Perl/Python, TCL, and Make About Meta Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics. Equal Employment Opportunity Meta is proud to be an Equal Employment Opportunity employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, reproductive health decisions, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, political views or activity, or other applicable legally protected characteristics. Meta is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture, or equivalent practical experience. 4 years of experience in RTL coding. Experience with methodologies for RTL quality checks (e.g., Lint, CDC, RDC). Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. Experience implementing Camera ISP image processing blocks, Video processing blocks, Machine Learning IPs, or other multimedia IPs such as Display or Video Codecs. Experience with ASIC design methodologies for clock domain checks and reset checks. About The Job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. The gChips team develops custom silicon solutions that provide differentiated user experiences in Google Hardware products and optimize performance and power for the aimed use cases. This includes SoCs (systems on a chip) and other mixed signal, logic, and sensor ICs (integrated circuits) for our product portfolio. Working with the product teams and other teams throughout Google, gChips maps out the silicon requirements looking ahead two to four years. In addition, it ensures the Hardware Product Area is up-to-date on the latest chip technologies and CPU, IO and memory standards. In this role, you will be part of a team that designs interconnect IP for Pixel System on a Chip (SoCs). You will collaborate with members of architecture, software, verification, power, timing, synthesis etc. to specify and deliver quality Register-Transfer Level (RTL). You will solve technical problems with micro-architecture, RTL, low power design methodology and evaluate design options with performance, power and area. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Collaborate with architects and develop microarchitecture. Perform Verilog/SystemVerilog RTL coding, functional/performance simulation debug and Lint/CDC/FV/UPF checks. Develop RTL implementations that meet engaged power, performance and area goals. Participate in synthesis, timing/power closure and support pre-silicon and post-silicon bring-up. Travel to other sites across the world to collaborate with global teams. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .

We are seeking highly motivated and talented VLSI Engineers with 2-4 years of industry experience to join our intensive Campus Training Program. This program is designed to provide in-depth, hands-on training in various aspects of VLSI design, verification, and implementation, specifically tailored to align with our current projects and future technological advancements. Upon successful completion of the training, candidates will transition into key roles within our VLSI design teams. This is an excellent opportunity for engineers looking to deepen their expertise, specialize in cutting-edge VLSI methodologies, and contribute to the development of next-generation semiconductor products. Responsibilities during the Training Program: * Actively participate in structured training modules covering advanced VLSI concepts, methodologies, and tools. * Engage in hands-on lab sessions and practical exercises to apply learned concepts. * Collaborate with trainers and mentors on assigned projects and case studies. * Complete individual and group assignments, demonstrating understanding and proficiency in VLSI sub-domains. * Participate in technical discussions, design reviews, and knowledge-sharing sessions. * Learn and adhere to industry best practices, design flows, and quality standards. * Continuously seek to improve technical skills and knowledge through self-study and provided resources. * Document progress, learning outcomes, and project work thoroughly. Key Areas of Training (may include, but are not limited to): * Digital IC Design: Advanced RTL design, low-power design techniques, clock domain crossing (CDC). * Verification: Advanced UVM/SystemVerilog methodologies, functional coverage, formal verification. * Physical Design: Floorplanning, placement, routing, clock tree synthesis (CTS), static timing analysis (STA), power integrity (PI) analysis. * Design for Testability (DFT): Scan insertion, ATPG, boundary scan. * Analog/Mixed-Signal Design (if applicable): Device physics, circuit simulation, layout considerations. * Front-End Tools: Synthesis, Linting, STA. * Back-End Tools: Place and Route, DRC/LVS. * Scripting: Perl, Python, TCL for automation. * EDA Tools: Exposure to industry-standard EDA tools from Cadence, Synopsys, Mentor Graphics (specific tools will be taught based on company needs). Required Qualifications: * Bachelor's or Master's degree in Electronics and Communication Engineering (ECE), Electrical Engineering (EE), or a related field. * 2-4 years of professional experience in VLSI design, verification, or physical design. * Strong fundamental understanding of digital electronics, circuit theory, and semiconductor physics. * Proficiency in at least one hardware description language (HDL) such as Verilog or VHDL. * Familiarity with the VLSI design flow (front-end to back-end). * Experience with scripting languages (e.g., Python, Perl, TCL) is highly desirable. * Excellent problem-solving and analytical skills. * Strong communication and interpersonal skills. * Ability to learn quickly and adapt to new technologies and methodologies. * Self-motivated with a strong desire to build a long-term career in VLSI. Preferred Qualifications (Assets): * Prior experience with specific EDA tools (Cadence Virtuoso, Synopsys DC/ICC/VCS, Mentor Graphics Calibre, etc.). * Experience with UVM methodology for verification. * Understanding of low-power design techniques. * Familiarity with formal verification concepts. * Exposure to advanced technology nodes.

Principal Physical Design Engineer Greater Bangalore -Hybrid/Hyderabad (Hybrid ) PrincipalPhysical Design Engineer Company Background We are a well-funded, stealth-mode startup based in Mountain View, CA, founded by senior technical and business executives hailing from category leaders in infrastructure semiconductors and hyperscale cloud services, and backed by top-tier investors with an immensely successful formula & track record on early-stage investments. We are a diverse team of expert chip/software/systems architects and developers who excel in hardware/software solution co-design. Our team has built, and delivered into production, technologies that process over half of the world's global data center traffic. Summary Join an ambitious and highly experienced team of silicon and hyperscale data center systems experts as a Physical Design Engineer. Our team is motivated by a singular mission: to revolutionize the performance and scalability of next-generation distributed computing infrastructure. You have the opportunity to build a groundbreaking new category of product, working alongside some of the industry's most talented hardware and software engineers to create truly disruptive infrastructure solutions that delight our customers. We are looking for talented, motivated engineers with experience in physically implementing large-scale networking and computing semiconductor products, and who are looking to grow in a fast paced, dynamic startup environment. We are looking for experienced physical design engineers who have the range to contribute across the full lifecycle of complex chip development, from CAD tool flow setup, early floorplan exploration in conjunction with microarchitecture development, through block partitioning, power planning, clock network design and construction, through P+R, timing closure, package design, PI/SI analysis, physical verification, and tapeout. Roles and Responsibilities Build and support the CAD tool flow for physical implementation in a cloud-first development environment. Work with architects and microarchitects on the chip-level floorplan and block partitioning. Evaluate tradeoffs in functional partitioning, block size, and interface complexity with other stakeholders. Define and construct the major physical structures, including the clock and reset architecture, the power delivery network, and interconnect topologies. Execute on block-level, cluster-level, and top-level physical implementation, from synthesis, floorplan and power plan, through P+R, through timing closure, physical verification, and tapeout. Interface with foundry and library partners on 3rd party IP and process technology issues, including updates to device models, IP integration requirements, and pre-tapeout signoff. Skills/Qualifications : Proven industry experience and successful track record in the physical implementation of large, high-performance network switching/routing fabrics (Ethernet, Infiniband, HPC), Network Interface Controllers, Smart-NICs, CPUs, or GPUs in the latest silicon process nodes. Deep experience with the latest CAD tools through the entire physical design workflow, e.g., Cadence Genus and Innovus, Synopsys ICC2/FusionCompiler, Tempus, PrimeTime SI, PrimeTime PX, StarRC, ICV, Calibre. Strong familiarity with various analysis tools such as Redhawk, Voltus. Experience with circuit analysis using HSPICE is a plus. Expert knowledge of SystemVerilog, as well as Perl, Python or other scripting languages. Minimum BSEE/CE + 15 years or MSEE/CE + 12 years experience. Proven track record of execution on products which have shipped in high-volume. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact The Data Centre Engineering Group develops Custom Silicon products tailored for the Data Centre market, focusing on cutting-edge Accelerated Infrastructure solutions for Networking, Switching, Connectivity, and Compute. The team works on high-performance and scalable architectures, ensuring optimized performance, power efficiency, and reliability to meet evolving data center demands. By collaborating across multiple teams, the group delivers best-in-class silicon solutions that drive innovation in next-generation data center applications. What You Can Expect Develop the architecture for a functional verification environment, including reference models, bus-functional monitors, and drivers Contribute to the development methodology and extend RoCE-related learnings within the team Write comprehensive verification test plans using random techniques and coverage analysis, in collaboration with design teams Develop test cases and tune the environment to meet coverage goals; debug failures and work with designers to resolve issues Verify boot code and architect, develop, and maintain tools to streamline the design of advanced multi-core SoCs Translate engineering requirements into scalable and user-friendly software tools optimized for highly parallel compute environments Perform unit and regression testing of developed software tools What We're Looking For BS in Computer Engineering, Electrical Engineering, or Computer Science with 15+ years of verification or design experience, or MS/PhD with 10+ years of experience Hands-on expertise in RoCE (RDMA over Converged Ethernet) Strong experience with SystemVerilog and UVM Proven ability to write detailed test plans and develop sophisticated directed and random verification environments Proficiency in scripting languages such as Python or Perl, and familiarity with EDA verification tools Experience with object-oriented design and implementation Good understanding of Linux operating systems Solid programming skills, especially in C++ and ARM assembly Working knowledge of high-speed Ethernet Understanding of other networking protocols is a plus Diligent, detail-oriented, and proactive, with the ability to manage tasks independently Open to feedback and able to work with diverse perspectives Flexible and adaptable; quick to learn in a fast-paced environment Additional Compensation And Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly skilled R&D Staff Engineer passionate about pushing the boundaries of static low power verification products. With 5 to 8 years of experience in software engineering, you have honed your expertise in C/C++ and possess a robust understanding of data structures and algorithms. Your background in Electronic Design Automation (EDA) tools and methodologies, coupled with your knowledge of Verilog, SystemVerilog, and VHDL, positions you as a leader in your field. You are a proactive problem-solver with a keen eye for detail, and you thrive in collaborative environments where you can lead and inspire a team. Your self-motivation and discipline drive you to set and achieve personal goals consistently, and your commitment to quality ensures that your contributions make a significant impact. Based in Noida or Bangalore, you are ready to take on new challenges and help shape the future of technology. What You’ll Be Doing: Designing and developing state-of-the-art EDA tools with innovative algorithms. Collaborating with local and remote teams to ensure seamless integration and execution. Working directly with customers to understand requirements, provide online debugging, and track delivery and execution. Leading a small team of 2-3 members, guiding them through technical challenges and project milestones. Contributing to the continuous improvement of our static low power verification product. Exploring new architectures and leading the charge in developing cutting-edge solutions. The Impact You Will Have: Driving the development of advanced EDA tools, contributing to the efficiency and effectiveness of chip design. Enhancing the quality and reliability of our static low power verification product. Providing critical support to customers, ensuring their needs are met and fostering long-term relationships. Leading and mentoring junior engineers, fostering a culture of innovation and excellence within the team. Contributing to Synopsys' reputation as a leader in the semiconductor and EDA industries. Playing a pivotal role in the successful execution of projects, meeting deadlines, and exceeding expectations. What You’ll Need: Fluency in C/C++ with a strong background in data structures and algorithms. Experience with UPF and familiarity with Tcl and Python-based development on Unix (preferred). Knowledge of Verilog, SystemVerilog, and VHDL HDL (preferred). Experience with production code development on Unix/Linux platforms. Ability to develop new architectures and demonstrate strong leadership skills. Who You Are: You are a dynamic and innovative engineer with a passion for technology and a commitment to quality. You possess excellent problem-solving skills and the ability to think critically and creatively. As a self-motivated individual, you set personal goals and work diligently to achieve them. Your leadership skills enable you to guide and inspire your team, fostering a collaborative and productive work environment. You are detail-oriented, ensuring that your work meets the highest standards of quality and reliability. Your experience in EDA tools and methodologies, coupled with your knowledge of hardware description languages, positions you as a valuable asset to our team. The Team You’ll Be A Part Of: You will be part of the Static Verification team, a group of talented engineers dedicated to developing and enhancing our static low power verification products. This team collaborates closely with other departments, including design, development, and customer support, to ensure seamless integration and execution. Together, you will work on cutting-edge projects that push the boundaries of technology and contribute to the success of Synopsys and its customers. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description Job Description We are seeking a highly skilled and experienced Staff Engineer for Functional Modeling & Verification to join our innovative team in Bengaluru, India. As a Staff Engineer, you will play a crucial role in shaping our technical direction, leading complex projects, and mentoring junior engineers. Lead architectural decisions and provide technical guidance to cross-functional teams Collaborate with product managers and other stakeholders to define technical requirements and solutions Conduct code reviews and ensure code quality across projects Mentor and guide junior engineers, fostering their professional growth Identify and resolve complex technical issues across multiple projects Stay current with emerging technologies and industry trends, recommending innovations to improve our tech stack Contribute to the development of engineering best practices and coding standards Participate in system design discussions and technical planning sessions Optimize existing systems for improved performance and scalability Hands-on experience in C++ & System C based Model development/test creation Prior Experience with C based Tests/Test bench development Python coding would be a plus Knowledge on NAND concepts will be an advantage Knowledge on Memory and Digital Design Concepts would be preferable (SRAM/DRAM/ROM/Flash) Circuits/Logic Participate in design / modeling reviews and provide technical guidance to junior engineers. Document all phases of Modeling releases and development for future reference and maintenance. Stay updated with the latest technologies and trends in NAND Flash and Modeling. Languages Expertise C, C++, Python, System C, SystemVerilog/UVM will be a plus Tool Expertise VisualStudio, Git, Bitbucket Hands-on contributions coding C++ & System C models & test creation Debug issues in Firmware environment Validating the developed model using SV/UVM testbench Debug failures and root-cause it by interacting with other teams/groups Etc. Qualifications Qualifications Bachelor's or Master's degree in Computer Science or a related field BE/BTech/ME/MTech in Engineering with Computer Science, ECE or related field MSc/MCA in Computer Science or a related field 13+ years of software engineering experience, with a proven track record of leading complex technical projects Expert-level proficiency in one or more programming languages such as Java, Python, or C++ Strong experience with cloud platforms (e.g., AWS, Azure, GCP) and distributed systems In-depth knowledge of system design, architecture, and performance optimization Proficiency in version control systems, preferably Git Ability to work effectively in a fast-paced, agile environment Strong analytical and detail-oriented approach to software development Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at jobs.accommodations@sandisk.com to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.

AI Centre Ethernet Switching Architect India-remote. person could be based anywhere in India - Remote work will be considered for exceptional profiles Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore AI Centre Ethernet Switching Architect Position Overview We are seeking a top-notch specialist Architect with over 20 years of experience to join our team in designing and developing Ethernet switches tailored for AI datacenter backend networks. The ideal candidate will have a strong background in digital design, ASIC/FPGA development, Ethernet/TCP/IP protocols, and experience with high-performance interconnect protocols such as InfiniBand, NVLink, Infinity Fabric, UALink, Ultra Ethernet with a focus on delivering high-performance, low-latency solutions for large-scale AI workloads. Key Responsibilities Define and develop the architecture of AI Datacentre Switch Fabric from ground up Performance Modelling and optimization of latency, throughput and power efficiency of switch fabric Decompose the architecture into sub blocks for implementation by design team Implement Ethernet protocols (IEEE 802.3, 100G/400G/800G/1600G), ECMP, and congestion control, packet spraying Apply knowledge of InfiniBand/Ultra Ethernet, NVLink/UALink, or similar protocols for feature implementation. Understanding/experience of IOS/Junos or equivalent software platform Use P4 or related languages for programmable packet processing. Working with design, software, verification team for complete product solutions Documentation of architecture and stay updated on AI networking trends. Required Qualifications Education: MS/PhD in Electrical/Electronic Engineering. Technical Skills: Proficient in Verilog/SystemVerilog for design. Knowledge of Ethernet (IEEE 802.3, 100G/400G/800G/1600G), ECMP, and congestion control. Experience with InfiniBand, NVLink, or similar protocols. Proficiency in P4 or programmable data plane languages. Knowledge of UALink, Ultra Ethernet, or RDMA/RoCE. Soft Skills: Strong problem-solving, communication, and teamwork skills. Position Overview Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We’re building high-performance RISC-V CPUs from the ground up, and we need someone who can help us test them thoroughly and thoughtfully. As a testbench lead, you'll design and maintain the infrastructure that makes sure our cores behave exactly as intended. If you enjoy figuring out how things break (and fixing them), building clean and reusable systems, and working with a team that values both rigor and creativity, we’d love to talk. This role is hybrid, based out of Bangalore. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are You’ve built and maintained testbenches for CPU cores or similar designs, using SystemVerilog, UVM, and C++. You like creating clean, reusable components — from transactors to functional models — that others can plug in and build on. You’re comfortable working across both software-style C++/UVM environments and hardware-style simulation flows. You enjoy collaborating with design teams and helping them debug issues quickly and clearly. What We Need Someone to design and grow a UVM testbench setup that works for both block-level and full-chip simulation. The ability to write C++ code that fits into a DV framework — and help shape that framework as it evolves. A good understanding of CPU microarchitecture and how to test it effectively. Comfort working across tools, from open-source simulators like Verilator to commercial environments and emulators. What You Will Learn How to design testbenches that scale with complexity — and keep them maintainable as the chip grows. How to support both simulation and emulation from the same DV infrastructure. How custom C++ and UVM environments can coexist to improve verification workflows. How different teams — RTL, DV, software, tools etc — come together to build AI-focused silicon. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set by the U.S. government. As this position will have direct and/or indirect access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and supporting documentation will be required and considered as a condition of employment. If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government. If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded.