850 Systemverilog Jobs - Page 8

Job Information Job Opening ID ZR_167_JOB Industry Semiconductor Date Opened 08/22/2025 Job Type Full time Work Experience 12+ Years City Bangalore / Hyderabad State/Province Karnataka / Telangana Country India Zip/Postal Code 560078 Job Description ASIC Verification Engineer – PCIe Expert (12+ years) Location: Bangalore / Hyderabad We are looking for an experienced ASIC Verification Engineer (12+ years) with a deep understanding and expertise of PCIe interface protocols (Gen1/2/3/4/5/6) . The ideal candidate thrives in dynamic environments where strong in SystemVerilog (SV) and UVM (Universal Verification Methodology) is highly valued. Key Responsibilities / What you’ll do: Deliver high-quality RTL and simulation models with strong focus on accuracy and efficiency. Develop, review, and execute verification plans and test environments at IP and/or SoC level. Apply a proactive, problem-solving mindset to complex design and verification challenges. Lead verification teams, mentor junior engineers, and interact and collaborate directly with customers to ensure seamless execution. Preferred Experience / What We’re Looking For: 12+ years of ASIC verification experience . Strong hands-on expertise in PCIe verification (IP or SoC level). Proven experience with UVM-based test benches and complex verification environments. Ability to work in collaborative, fast-paced environments with a commitment to quality, innovation and technical leadership .

Project description We are passionate about transforming lives through cutting-edge technology, enriching industries, communities, and the world. Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the world's most critical problems. We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way. Responsibilities Develop, implement, and maintain verification environments using Verilog/SystemVerilog. Apply UVM methodology to build and enhance testbenches, ensuring thorough coverage of verification scenarios. Perform debugging and root-cause analysis of test failures to ensure design quality. Verify and validate AMBA protocols (AXI, AHB, APB) where applicable. Collaborate on ARM-based SoC verification tasks (preferred, but not mandatory). Leverage strong knowledge of digital design fundamentals to identify design and verification gaps. Create and maintain automation scripts (Perl, Tcl, Make, Shell scripting) to improve verification efficiency. Work closely with design, validation, and architecture teams to ensure timely closure of verification tasks. Skills Must have 8+yrs exp Strong verification skills with hands-on experience in Verilog and SystemVerilog. Proven expertise in UVM methodology, with solid experience in developing testbenches. Good debugging and problem-solving skills. Familiarity with AMBA protocols (AXI, AHB, APB) good to have. Strong foundation in digital design fundamentals. Proficiency in scripting languages (Perl, Tcl, Make, Shell scripting) for automation. Nice to have Exposure to ARM-based SoCs preferred but not mandatory. Other Languages English: B2 Upper Intermediate Seniority Senior Hyderabad, IN, India Req. VR-116865 Manual Testing Automotive Industry 22/08/2025 Req. VR-116865

Project description We are passionate about transforming lives through cutting-edge technology, enriching industries, communities, and the world. Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the world's most critical problems. We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way. Responsibilities Develop, implement, and maintain verification environments using Verilog/SystemVerilog. Apply UVM methodology to build and enhance testbenches, ensuring thorough coverage of verification scenarios. Perform debugging and root-cause analysis of test failures to ensure design quality. Verify and validate AMBA protocols (AXI, AHB, APB) where applicable. Collaborate on ARM-based SoC verification tasks (preferred, but not mandatory). Leverage strong knowledge of digital design fundamentals to identify design and verification gaps. Create and maintain automation scripts (Perl, Tcl, Make, Shell scripting) to improve verification efficiency. Work closely with design, validation, and architecture teams to ensure timely closure of verification tasks. Skills Must have 8+yrs exp Strong verification skills with hands-on experience in Verilog and SystemVerilog. Proven expertise in UVM methodology, with solid experience in developing testbenches. Good debugging and problem-solving skills. Familiarity with AMBA protocols (AXI, AHB, APB) good to have. Strong foundation in digital design fundamentals. Proficiency in scripting languages (Perl, Tcl, Make, Shell scripting) for automation. Nice to have Exposure to ARM-based SoCs preferred but not mandatory. Other Languages English: B2 Upper Intermediate Seniority Senior Bengaluru, India Req. VR-116865 Manual Testing Automotive Industry 22/08/2025 Req. VR-116865

Principal IP/RTL Design Engineer for TPU / GPU Hyderabad / Bangalore Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. Position Overview Seeking an IP/RTL Design Engineer with 5+ years of experience to design IP/RTL for TPUs, focusing on high-performance matrix multiplication, low-latency interconnects, and power-efficient AI acceleration. Key Responsibilities Design IP blocks for TPU cores, including systolic arrays, vector units, and memory subsystems. Develop Verilog/SystemVerilog RTL for performance, timing, and area optimization. Implement high-speed interconnects (e.g., AXI, NoC) for TPU / /GPU. data pipelines. Optimize designs for high throughput, low latency, and power efficiency in AI workloads. Integrate LPDDR6, HBM3, DDR5, or chiplet-based memory interfaces. Support synthesis, timing closure, and FPGA prototyping and Design Verification team Document microarchitecture and design specifications. Required Qualifications Education: BS/MS in Electrical/Computer Engineering. Experience: 10+ years in ASIC/FPGA IP/RTL design, with 3+ years in AI accelerators or GPU / TPU-like architectures. Skills: Proficient in Verilog/SystemVerilog RTL design. Knowledge of GPU/TPU architectures, systolic arrays, or matrix multiplication units. Experience with AXI, NoC, or similar interconnect protocols. Familiarity with LPDDR6, HBM3, DDR5, or high-bandwidth memory interfaces. Proficiency with synthesis and timing tools (e.g., Synopsys Design Compiler). Strong problem-solving and teamwork skills. Preferred Qualifications Experience with AI/ML workloads or datacenter TPU designs and GPU architectures Knowledge of CXL, PCIe, UALink, or Ultra Ethernet. Familiarity with power optimization for high-performance chips. What is in it for you? Pure play product work environment Chance to work with a tightly knit group of exceptional engineers who come from the top companies of the Semiconductor world Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. A meritocracy first work place where each peer is a star A chance to be a part of industry shaping product in entirety (not bits and pieces) from initial stages A chance to work at a startup which already has customers and investor lined up for their product pipeline (We do not have a marketing/sales team, because we do not need them). A chance to learn from industry veterans who have already launched multiple Billion Dollar Semiconductor firms over the last 3 decades. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Location: Bengaluru, Karnataka Experience: Minimum 3 Years of EdTech/IT/Corporate/Institutions Qualification: BE, BTECH, ME, MTECH, MCA (Any Degree) Shift Timing: 9:00 am to 6:00 pm (Mon to Fri) 9:00 am to 1:00 pm ( Sat) Skills & Requirements: Outstanding verbal and written communication skills, along with strong negotiation abilities Proficient in spoken English – fluency is a must Solid experience in delivering technical training, especially in areas such as VLSI, Verilog, HDL, VHDL, Digital/Analog/Physical Electronics, and Verification Hands-on expertise in Verilog programming, Linux OS, Digital System Design, SystemVerilog (SV), UVM, and FPGA Understanding of academic institution operations and placement procedures Strong interpersonal skills with a well-established professional network Familiarity with multi-tier architecture concepts Excellent organizational skills, including task management, prioritization, and reporting Commitment to delivering quality training on time A proactive attitude towards understanding business objectives Roles & Responsibilities: Deliver in-depth technical training sessions to students, professionals, and corporate participants Design and develop tailored course content, assessments, and training materials Conduct technical workshops for colleges and corporate clients Supervise and mentor students on hands-on projects and group activities Manage the full training cycle—from needs assessment to program evaluation Ensure effective and high-quality training outcomes Collaborate with stakeholders to align training programs with organizational goals Monitor and maintain delivery standards across all batches Provide constructive feedback and assess learner performance for continuous improvement Job Type: Full-time Pay: ₹35,000.00 - ₹65,000.00 per month Education: Bachelor's (Preferred) Experience: VLSI Trainer: 3 years (Preferred) Verilog: 3 years (Preferred) Language: English (Preferred) Work Location: In person

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and skilled R&D Engineer with a deep understanding of system verification. You are enthusiastic about developing cutting-edge verification solutions for high-performance computing, data centers, mobile/client devices, automotive systems, and IoT segments. Your experience in architecting and building SystemVerilog UVM-based verification components, coupled with your expertise in cache coherency protocols and functional verification, makes you an ideal candidate for this role. You are a team player with excellent problem-solving abilities, strong analytical skills, and a keen attention to detail. Your background in verification IP development and your programming prowess in languages like Perl, Python, and Shell scripting set you apart as a valuable asset to our team. What You’ll Be Doing: Responsible for functional verification involving coherent and non-coherent IP designs. Collaborating with market leaders in High Performance Computing, Data Centre, Mobile/Client, Automotive, and IoT segments to define and develop products that meet complex verification requirements. Architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. Developing verification plans and driving functional coverage-driven verification closure of real designs. Debugging and resolving issues in verification environments to ensure robust and reliable verification processes. The Impact You Will Have: Enhancing the reliability and performance of high-performance computing and data center systems through rigorous verification processes. Contributing to the advancement of mobile and client devices by ensuring the integrity and functionality of their verification protocols. Driving innovation in the automotive sector by developing robust verification solutions for automotive systems. Supporting the growth of IoT applications by providing reliable and efficient verification for IoT devices. Collaborating with industry leaders to shape the future of system verification and contribute to technological advancements. Ensuring the successful implementation and integration of verification IPs, thereby enhancing the overall quality of our products. What You’ll Need: B.E/B.Tech in Electrical Engineering/Electronics & Communications Engineering with 8-12 years of relevant experience, OR M.E/M.Tech in VLSI Design/Microelectronics with 6-10 years of relevant experience. Hands-on experience in architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. In-depth understanding of cache coherency protocols such as Protocol experience: Should have experience in any of the protocols, UCIe/PCIe/CXL/Unipro/USB/MIPI/HDMI/Ethernet/DDR/LPDDR/HBM memory protocol Experience in creating verification plans and achieving functional coverage-driven verification closure of real designs. Proficiency in writing scripts using Perl, Python, and Shell scripting. Who You Are: Excellent problem-solving, debugging, and analytical skills. Strong programming skills and familiarity with object-oriented programming concepts. Creative and innovative mindset. Excellent verbal and written communication skills. A collaborative team player with a passion for functional verification.

Principal Staff Verification Engineer (VLSI Verification + AV +AI Expertise) Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. Thu, Aug 21 at 4:49 PM Job Description – Staff Verification Engineer (VLSI Verification + AV +AI Expertise) Position: Staff Verification Engineer – VLSI Verification Lead Location: Hyderabad Experience: 12+ years in Functional Verification Key Protocol Experience: MIPI DSI, DisplayPort, HDMI Role Overview We are seeking a highly skilled Staff Verification Engineer with strong expertise in VLSI functional verification and a good understanding of AI model deployment for Audio/Video applications. The candidate will lead verification efforts for complex SoCs/IPs, while also collaborating with cross-functional teams on next-generation multimedia and AI-driven system use cases. Requirements Experience: 12+ years in functional verification; minimum 5+ years in Multimedia (Display, Camera, Video, Graphics) domain . Domain Expertise: Strong knowledge in Display (Pixel processing, composition, compression, MIPI DSI, DisplayPort, HDMI) and Bus/Interconnect (AHB, AXI). Multimedia technologies: Audio/Video codecs, Image Processing, SoC system use cases (Display, Camera, Video, Graphics). Good understanding of DSP, codecs (audio/video), and real-time streaming pipelines. AI accelerators – architecture understanding, verification, and deployment experience across NPUs, GPUs, and custom AI engines. SoC system-level verification with embedded RISC/DSP processors. AI/ML Skills: Experience with AI models (ex. CNN ) and statistical modeling techniques. Exposure to audio frameworks, audio solutions, and embedded platforms. Hands-on in multimedia use cases verification and system-level scenarios. Strong exposure to MIPI DSI-2, CSI-2, MIPI D-PHY, C-PHY. Verification Expertise: Proven expertise in developing/maintaining SystemVerilog/UVM-based testbenches, UVCs, sequences, checkers, coverage models. Strong understanding of OOP concepts in verification. HVL: SystemVerilog (UVM), SystemC (preferred). HDL: Verilog, SystemVerilog. Leadership & Collaboration: Mentor and guide junior verification engineers; drive closure for IP and SoC-level deliverables. Strong written and verbal communication skills; ability to convey complex technical concepts. Proven ability to plan, prioritize, and execute effectively. Debugging & Architecture Knowledge: Excellent debug skills across SoC architecture, VIP integration, and verification flows. Responsibilities AI & Multimedia (AV) Responsibilities Develop, optimize, and deploy AI models for audio and video applications, with strong focus on inference efficiency and performance optimization across NPUs, GPUs, and CPUs. Perform model evaluation, quantization, and compression to enable fast and robust inference on embedded hardware. Collaborate with cross-functional R&D, systems, and integration teams for system use case verification and commercialization support. Evaluate system performance, debug, and optimize for robustness and efficiency. Participate in industry benchmarking and trend analysis; introduce state-of-the-art architectural and technical innovations. ASIC / SoC Verification Responsibilities Lead and contribute to feature, core, and subsystem verification during ASIC design and development phases through RTL and Gate-Level simulations. Collaborate with the design team to define verification requirements, ensuring functional, performance, and power correctness. Develop and execute comprehensive test plans and drive verification closure. Create and maintain SystemVerilog/UVM testbenches, assertions, and functional coverage models. Implement and enhance automation flows to improve verification efficiency. Participate in debug activities throughout the development cycle. Apply ASIC expertise to define, model, optimize, verify, and validate IP (block/SoC) development for high-performance, low-power products. Collaborate with software and hardware architecture teams to develop strategies meeting system-level requirements. Evaluate complete design flows from RTL through synthesis, place-and-route, timing, and power usage. Write detailed technical documentation for verification methodologies, flows, and deliverables. Contact: Uday Bhaskar Mulya Technologies "Mining the Knowledge Community" Email id : muday_bhaskar@yahoo.com

DESCRIPTION As a Design Verification Manager, you will contribute to exploring innovative hardware designs to enhance our devices. You will define verification methodology and implement test plans for advanced functional blocks while collaborating with cross-functional teams to develop world-class hardware devices. You will participate in the bringup of such blocks on Simulation and Emulation platforms. You will work closely with multi-disciplinary groups including Architecture, RTL Design, PD, Validation, Software and Product Design to architect and implement verification environments for complex functional block that enable development of world-class hardware devices. In this role, you will: . Architect and implement verification environments for complex functional blocks . Create and enhance verification environments using SystemVerilog and UVM . Develop comprehensive test plans through collaboration with design engineers, SW and architects . Implement coverage measures for stimulus and corner-case scenarios . Participate in test plan and coverage reviews . Drive complex RTL and TB debugs . Drive UPF based low power verification . Contribute to verification activities across simulation and emulation platforms . Work on creating the automation scripts to support DV methodologies . Create infrastructure to performs system level performance analysis . Manage a team of 6-8 DV Engineers BASIC QUALIFICATIONS . Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science, or equivalent . 10+ years or more of practical semiconductor ASIC experience including owning end to end DV of major SOC blocks . Managing a team of DV Engineers . Experience with RTL development environments . Proficiency in hardware description languages and verification methodologies . Experience verifying complex IP blocks integrated into SOCs . Knowledge of verification platforms including UVM, emulation, and FPGA . Demonstrated success in test plan development and verification infrastructure . Experience with industry-standard tools and scripting languages (Python or Perl) . Understanding of object-oriented programming concepts PREFERRED QUALIFICATIONS . Advanced degrees in Computer Science, Electrical Engineering, or related field . Experience with ARM and DSP instruction set architectures . Expertise in system-level debugging . Strong programming skills in SV, UVM and C . Knowledge of AMBA bus protocols . Experience with formal verification methods . Experience with Low power verification methods . Experience with Baremetal processor environments . Transaction level modelling expertise . Familiarity with industry standard I/O interfaces . FPGA and emulation platform knowledge . Understanding of SoC architecture . Strong verbal and written communication abilities Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit for more information. If the country/region you're applying in isn't listed, please contact your Recruiting Partner.

DESCRIPTION As a Senior Design Verification Engineer, you will contribute to exploring innovative hardware designs to enhance our devices. You will define verification methodology and implement test plans for advanced functional blocks while collaborating with cross-functional teams to develop world-class hardware devices. You will participate in the bringup of such blocks on Simulation and Emulation platforms. You will work closely with multi-disciplinary groups including Architecture, RTL Design, PD, Validation, Software and Product Design to architect and implement verification environments for complex functional block that enable development of world-class hardware devices. In this role, you will: . Architect and implement verification environments for complex functional blocks . Create and enhance verification environments using SystemVerilog and UVM . Develop comprehensive test plans through collaboration with design engineers, SW and architects . Implement coverage measures for stimulus and corner-case scenarios . Participate in test plan and coverage reviews . Drive complex RTL and TB debugs . Drive UPF based low power verification . Contribute to verification activities across simulation and emulation platforms . Work on creating the automation scripts to support DV methodologies . Create infrastructure to performs system level performance analysis BASIC QUALIFICATIONS . Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science, or equivalent . 10+ years or more of practical semiconductor ASIC experience including owning end to end DV of major SOC blocks . Experience with RTL development environments . Proficiency in hardware description languages and verification methodologies . Experience verifying complex IP blocks integrated into SOCs . Knowledge of verification platforms including UVM, emulation, and FPGA . Demonstrated success in test plan development and verification infrastructure . Experience with industry-standard tools and scripting languages (Python or Perl) . Understanding of object-oriented programming concepts PREFERRED QUALIFICATIONS . Advanced degrees in Computer Science, Electrical Engineering, or related field . Experience with ARM and DSP instruction set architectures . Expertise in system-level debugging . Strong programming skills in SV, UVM and C . Knowledge of AMBA bus protocols . Experience with formal verification methods . Experience with Low power verification methods . Experience with Baremetal processor environments . Transaction level modelling expertise . Familiarity with industry standard I/O interfaces . FPGA and emulation platform knowledge . Understanding of SoC architecture . Strong verbal and written communication abilities Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit for more information. If the country/region you're applying in isn't listed, please contact your Recruiting Partner.

Responsibilities Define and implement test plans and verification plans based on specifications and requirements.(10%) Develop assertion-based checkers and functional coverage metrics based on verifications plans.(20%) Perform functional verification of RTL designs using industry-standard tools and methodologies.(20%) Generate and analyze coverage reports to ensure thorough verification.(20%) Collaborate with design and architecture teams to understand design specifications and requirements.(10%) Identify and resolve verification issues and bugs.(10%) Continuously improve verification processes and methodologies.(10%) Minimum Qualifications Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. Minimum 6 years of experience in SOC verification. Hands-on verification experience using UVM methodology Strong understanding of test and verification plan definition and implementation. Experience with coverage-driven verification and coverage report generation. Familiarity with industry-standard verification tools (e.g.,VCS, QuestaSim). Experience with IC design verification. Knowledge of HDL methodology with the most recent experience in UVM. Proficiency in SystemVerilog and assertion-based verification. Experience with formal verification. Hands-on verification experience of Bus Fabric, NOC, AMBA-AHB/AXI based bus architecture in a UVM environment. Knowledge of Low Power Verification Excellent problem-solving skills and attention to detail. Strong communication and teamwork skills. Desired Qualifications Strong knowledge in Python programming Experience in wireless SoC design and verification. Knowledge of scripting languages (e.g., TCL, Python, Perl) for automation. Familiarity with version control systems (e.g., Git).

Responsibilities Define and implement test plans and verification plans based on specifications and requirements.(10%) Develop assertion-based checkers and functional coverage metrics based on verifications plans.(20%) Perform functional verification of RTL designs using industry-standard tools and methodologies.(20%) Generate and analyze coverage reports to ensure thorough verification.(20%) Collaborate with design and architecture teams to understand design specifications and requirements.(10%) Identify and resolve verification issues and bugs.(10%) Continuously improve verification processes and methodologies.(10%) Minimum Qualifications Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. Minimum 4 years of experience in SOC verification. Hands-on verification experience using UVM methodology Strong understanding of test and verification plan definition and implementation. Experience with coverage-driven verification and coverage report generation. Familiarity with industry-standard verification tools (e.g.,VCS, QuestaSim). Experience with IC design verification. Knowledge of HDL methodology with the most recent experience in UVM. Proficiency in SystemVerilog and assertion-based verification. Experience with formal verification. Hands-on verification experience of Bus Fabric, NOC, AMBA-AHB/AXI based bus architecture in a UVM environment. Knowledge of Low Power Verification Excellent problem-solving skills and attention to detail. Strong communication and teamwork skills. Desired Qualifications Strong knowledge in Python programming Experience in wireless SoC design and verification. Knowledge of scripting languages (e.g., TCL, Python, Perl) for automation. Familiarity with version control systems (e.g., Git).

Responsibilities Define and implement test plans and verification plans based on specifications and requirements.(10%) Develop assertion-based checkers and functional coverage metrics based on verifications plans.(20%) Perform functional verification of RTL designs using industry-standard tools and methodologies.(20%) Generate and analyze coverage reports to ensure thorough verification.(20%) Collaborate with design and architecture teams to understand design specifications and requirements.(10%) Identify and resolve verification issues and bugs.(10%) Continuously improve verification processes and methodologies.(10%) Minimum Qualifications Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. Minimum 6 years of experience in SOC verification. Hands-on verification experience using UVM methodology Strong understanding of test and verification plan definition and implementation. Experience with coverage-driven verification and coverage report generation. Familiarity with industry-standard verification tools (e.g.,VCS, QuestaSim). Experience with IC design verification. Knowledge of HDL methodology with the most recent experience in UVM. Proficiency in SystemVerilog and assertion-based verification. Experience with formal verification. Hands-on verification experience of Bus Fabric, NOC, AMBA-AHB/AXI based bus architecture in a UVM environment. Knowledge of Low Power Verification Excellent problem-solving skills and attention to detail. Strong communication and teamwork skills. Desired Qualifications Strong knowledge in Python programming Experience in wireless SoC design and verification. Knowledge of scripting languages (e.g., TCL, Python, Perl) for automation. Familiarity with version control systems (e.g., Git).

Principal Staff Verification Engineer (VLSI Verification + AV +AI Expertise) Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. Thu, Aug 21 at 4:49 PM Job Description – Staff Verification Engineer (VLSI Verification + AV +AI Expertise) Position: Staff Verification Engineer – VLSI Verification Lead Location: Hyderabad Experience: 12+ years in Functional Verification Key Protocol Experience: MIPI DSI, DisplayPort, HDMI Role Overview We are seeking a highly skilled Staff Verification Engineer with strong expertise in VLSI functional verification and a good understanding of AI model deployment for Audio/Video applications. The candidate will lead verification efforts for complex SoCs/IPs, while also collaborating with cross-functional teams on next-generation multimedia and AI-driven system use cases. Requirements Experience: 12+ years in functional verification; minimum 5+ years in Multimedia (Display, Camera, Video, Graphics) domain . Domain Expertise: Strong knowledge in Display (Pixel processing, composition, compression, MIPI DSI, DisplayPort, HDMI) and Bus/Interconnect (AHB, AXI). Multimedia technologies: Audio/Video codecs, Image Processing, SoC system use cases (Display, Camera, Video, Graphics). Good understanding of DSP, codecs (audio/video), and real-time streaming pipelines. AI accelerators – architecture understanding, verification, and deployment experience across NPUs, GPUs, and custom AI engines. SoC system-level verification with embedded RISC/DSP processors. AI/ML Skills: Experience with AI models (ex. CNN ) and statistical modeling techniques. Exposure to audio frameworks, audio solutions, and embedded platforms. Hands-on in multimedia use cases verification and system-level scenarios. Strong exposure to MIPI DSI-2, CSI-2, MIPI D-PHY, C-PHY. Verification Expertise: Proven expertise in developing/maintaining SystemVerilog/UVM-based testbenches, UVCs, sequences, checkers, coverage models. Strong understanding of OOP concepts in verification. HVL: SystemVerilog (UVM), SystemC (preferred). HDL: Verilog, SystemVerilog. Leadership & Collaboration: Mentor and guide junior verification engineers; drive closure for IP and SoC-level deliverables. Strong written and verbal communication skills; ability to convey complex technical concepts. Proven ability to plan, prioritize, and execute effectively. Debugging & Architecture Knowledge: Excellent debug skills across SoC architecture, VIP integration, and verification flows. Responsibilities AI & Multimedia (AV) Responsibilities Develop, optimize, and deploy AI models for audio and video applications, with strong focus on inference efficiency and performance optimization across NPUs, GPUs, and CPUs. Perform model evaluation, quantization, and compression to enable fast and robust inference on embedded hardware. Collaborate with cross-functional R&D, systems, and integration teams for system use case verification and commercialization support. Evaluate system performance, debug, and optimize for robustness and efficiency. Participate in industry benchmarking and trend analysis; introduce state-of-the-art architectural and technical innovations. ASIC / SoC Verification Responsibilities Lead and contribute to feature, core, and subsystem verification during ASIC design and development phases through RTL and Gate-Level simulations. Collaborate with the design team to define verification requirements, ensuring functional, performance, and power correctness. Develop and execute comprehensive test plans and drive verification closure. Create and maintain SystemVerilog/UVM testbenches, assertions, and functional coverage models. Implement and enhance automation flows to improve verification efficiency. Participate in debug activities throughout the development cycle. Apply ASIC expertise to define, model, optimize, verify, and validate IP (block/SoC) development for high-performance, low-power products. Collaborate with software and hardware architecture teams to develop strategies meeting system-level requirements. Evaluate complete design flows from RTL through synthesis, place-and-route, timing, and power usage. Write detailed technical documentation for verification methodologies, flows, and deliverables. Contact: Uday Bhaskar Mulya Technologies "Mining the Knowledge Community" Email id : muday_bhaskar@yahoo.com

Principal Staff Verification Engineer (VLSI Verification + AV +AI Expertise) Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. Thu, Aug 21 at 4:49 PM Job Description – Staff Verification Engineer (VLSI Verification + AV +AI Expertise) Position: Staff Verification Engineer – VLSI Verification Lead Location: Hyderabad Experience: 12+ years in Functional Verification Key Protocol Experience: MIPI DSI, DisplayPort, HDMI Role Overview We are seeking a highly skilled Staff Verification Engineer with strong expertise in VLSI functional verification and a good understanding of AI model deployment for Audio/Video applications. The candidate will lead verification efforts for complex SoCs/IPs, while also collaborating with cross-functional teams on next-generation multimedia and AI-driven system use cases. Requirements Experience: 12+ years in functional verification; minimum 5+ years in Multimedia (Display, Camera, Video, Graphics) domain . Domain Expertise: Strong knowledge in Display (Pixel processing, composition, compression, MIPI DSI, DisplayPort, HDMI) and Bus/Interconnect (AHB, AXI). Multimedia technologies: Audio/Video codecs, Image Processing, SoC system use cases (Display, Camera, Video, Graphics). Good understanding of DSP, codecs (audio/video), and real-time streaming pipelines. AI accelerators – architecture understanding, verification, and deployment experience across NPUs, GPUs, and custom AI engines. SoC system-level verification with embedded RISC/DSP processors. AI/ML Skills: Experience with AI models (ex. CNN ) and statistical modeling techniques. Exposure to audio frameworks, audio solutions, and embedded platforms. Hands-on in multimedia use cases verification and system-level scenarios. Strong exposure to MIPI DSI-2, CSI-2, MIPI D-PHY, C-PHY. Verification Expertise: Proven expertise in developing/maintaining SystemVerilog/UVM-based testbenches, UVCs, sequences, checkers, coverage models. Strong understanding of OOP concepts in verification. HVL: SystemVerilog (UVM), SystemC (preferred). HDL: Verilog, SystemVerilog. Leadership & Collaboration: Mentor and guide junior verification engineers; drive closure for IP and SoC-level deliverables. Strong written and verbal communication skills; ability to convey complex technical concepts. Proven ability to plan, prioritize, and execute effectively. Debugging & Architecture Knowledge: Excellent debug skills across SoC architecture, VIP integration, and verification flows. Responsibilities AI & Multimedia (AV) Responsibilities Develop, optimize, and deploy AI models for audio and video applications, with strong focus on inference efficiency and performance optimization across NPUs, GPUs, and CPUs. Perform model evaluation, quantization, and compression to enable fast and robust inference on embedded hardware. Collaborate with cross-functional R&D, systems, and integration teams for system use case verification and commercialization support. Evaluate system performance, debug, and optimize for robustness and efficiency. Participate in industry benchmarking and trend analysis; introduce state-of-the-art architectural and technical innovations. ASIC / SoC Verification Responsibilities Lead and contribute to feature, core, and subsystem verification during ASIC design and development phases through RTL and Gate-Level simulations. Collaborate with the design team to define verification requirements, ensuring functional, performance, and power correctness. Develop and execute comprehensive test plans and drive verification closure. Create and maintain SystemVerilog/UVM testbenches, assertions, and functional coverage models. Implement and enhance automation flows to improve verification efficiency. Participate in debug activities throughout the development cycle. Apply ASIC expertise to define, model, optimize, verify, and validate IP (block/SoC) development for high-performance, low-power products. Collaborate with software and hardware architecture teams to develop strategies meeting system-level requirements. Evaluate complete design flows from RTL through synthesis, place-and-route, timing, and power usage. Write detailed technical documentation for verification methodologies, flows, and deliverables. Contact: Uday Bhaskar Mulya Technologies "Mining the Knowledge Community" Email id : muday_bhaskar@yahoo.com

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: SE NIOR SILICON DESIGN ENGINEER THE ROLE : We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The Verification Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Develop/Maintain tests for functional verification and performance verification at the core level Build testbench components to support the next generation IP Maintain or improve current test libraries to support IP level testing Create hardware emulation build to verify the IP functional performance Maintain and improve current hardware emulation environment to speed up the runtime performance and improve the debug facility Provide technical support to other teams PREFERRED EXPERIENCE: Good at C/C++ Familiarity with SystemVerilog and modern verification libraries like UVM Experience/Background on Computing/Graphics is a benefit Experience with OpenGL/OpenCL/D3D programming is a benefit ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-PK2 Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Category Engineering Hire Type Employee Job ID 10795 Remote Eligible No Date Posted 20/04/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and skilled R&D Engineer with a deep understanding of system verification. You are enthusiastic about developing cutting-edge verification solutions for high-performance computing, data centers, mobile/client devices, automotive systems, and IoT segments. Your experience in architecting and building SystemVerilog UVM-based verification components, coupled with your expertise in cache coherency protocols and functional verification, makes you an ideal candidate for this role. You are a team player with excellent problem-solving abilities, strong analytical skills, and a keen attention to detail. Your background in verification IP development and your programming prowess in languages like Perl, Python, and Shell scripting set you apart as a valuable asset to our team. What You’ll Be Doing: Responsible for functional verification involving coherent and non-coherent IP designs. Collaborating with market leaders in High Performance Computing, Data Centre, Mobile/Client, Automotive, and IoT segments to define and develop products that meet complex verification requirements. Architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. Developing verification plans and driving functional coverage-driven verification closure of real designs. Debugging and resolving issues in verification environments to ensure robust and reliable verification processes. The Impact You Will Have: Enhancing the reliability and performance of high-performance computing and data center systems through rigorous verification processes. Contributing to the advancement of mobile and client devices by ensuring the integrity and functionality of their verification protocols. Driving innovation in the automotive sector by developing robust verification solutions for automotive systems. Supporting the growth of IoT applications by providing reliable and efficient verification for IoT devices. Collaborating with industry leaders to shape the future of system verification and contribute to technological advancements. Ensuring the successful implementation and integration of verification IPs, thereby enhancing the overall quality of our products. What You’ll Need: B.E/B.Tech in Electrical Engineering/Electronics & Communications Engineering with 8-12 years of relevant experience, OR M.E/M.Tech in VLSI Design/Microelectronics with 6-10 years of relevant experience. Hands-on experience in architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. In-depth understanding of cache coherency protocols such as Protocol experience: Should have experience in any of the protocols, UCIe/PCIe/CXL/Unipro/USB/MIPI/HDMI/Ethernet/DDR/LPDDR/HBM memory protocol Experience in creating verification plans and achieving functional coverage-driven verification closure of real designs. Proficiency in writing scripts using Perl, Python, and Shell scripting. Who You Are: Excellent problem-solving, debugging, and analytical skills. Strong programming skills and familiarity with object-oriented programming concepts. Creative and innovative mindset. Excellent verbal and written communication skills. A collaborative team player with a passion for functional verification. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Expertise in UVM and System Verilog Experience in verification IP modelling with knowledge of test case coding, scoreboard design, assertions, checkers & functional coverage. Involved & played a driving role in the development of reusable Verification environments for at least 2 verification projects using VMM/OVM/UVM methodologies. Protocol experience: Should have experience on UCIe / PCIe / CXL / Unipro / USB / MIPI / HDMI / Ethernet / DDR / LPDDR / HBM memory protocol Job responsibilities: Able to contribute to the development of the VIP Responsible & can be relied on for review sign-off of VIP development and updates from a technical perspective including methodology and protocol functional prospective. Liaison with Architects/methodology experts to achieve resolutions on issues or driving output from an architecture/methodology perspective Locally should be to be go-to person on all technical aspects of VIP

The candidate will be part of the Synopsys CXL IP Design verification R&D team at Synopsys. You will own UVM based verification environment, which handles multiple features of IP, test plan creation, test case writing, random constraint creation, coverage closure, SVA and Release. As part of the work, you will closely work with lead and be part of a global team of experienced engineers. Technical Expertise Needed: BS or MS degree in Computer Science, Electrical or Electronics Engineering, or Related Field with 8+ years of experience in the following areas: Own UVM based testbench environment and developed UVM testbench architecture, Testplan and SVA for an IP. Knowledge of one or more of protocols/standards: PCIe, CXL, UCIe, AMBA (AXI,APB,AHB) etc Good knowledge of System Verilog. Hands-on experience with coverage closure and writing SVA for IP/SOC. Good simulation debugging skills. Experience with Perforce or similar revision control environment. Experience with Python/TCL or any scripting knowledge is an added advantage. Job Responsibilities include - Understand Standard Specifications, create testplan for the product and create UVM based testbench architecture. Propose and enhance the UVM architecture with unique idea for verification. Be single point of contact with hands-on experience on all verification tasks - Testbench Creation - Testplan creation - Coverage closure - SVA - Release Perform peer review of testbench code for continuous quality. Own simulation debugs using DVE/Verdi, interact with Design Team and aid in debug and Verification closure. The candidate will work in a project and team-oriented environment with teams spread across multiple sites, worldwide. Lead team of engineers to perform various verification activities on IPs/Subsystems. Anticipate problems and risks and work towards a resolution and risk mitigation plan. Assist and mentor the team in day-to-day activities and grow the capabilities of verification team for future assignments. Review various results and reports to provide continuous feedback to the team and improve quality of deliverables. Report status to management and provide suggestions to resolve any issues that may impact execution. The candidate must have excellent oratory and written communication skills in English, should be a team player and possess good problem-solving skills and show high levels of initiative.

Here's the revised description with bullets and bolded subheadings: You are a seasoned engineer with a passion for pushing the boundaries of technology. With 8-15 years of experience, you bring a wealth of knowledge in software architecture and leadership. You excel in C/C++ software development, and your strong background in design patterns, data structures, and algorithms sets you apart. You thrive in multi-threaded and distributed code environments, and your familiarity with ASIC design flow and EDA tools is second to none. Your expertise in Verilog, SystemVerilog, and VHDL HDL, coupled with your experience in Unix/Linux platforms, makes you a valuable asset. You are well-versed in developer tools like gdb and Valgrind, and you understand the importance of source code control tools such as Perforce. Your analytical and problem-solving skills are top-notch, and you are always eager to learn and explore new technologies. As a highly enthusiastic and energetic team player, you are ready to go the extra mile to achieve success. What You'll Be Doing: Designing, developing, and troubleshooting core algorithms for word-level synthesis. Collaborating with local and global teams to enhance synthesis QoR, performance, and logic interference. Engaging in pure technical roles focused on software development and architecture. Implementing multi-threaded and distributed code solutions. Utilizing your knowledge of ASIC design flow and EDA tools to drive innovation. Leveraging your expertise in Verilog, SystemVerilog, and VHDL HDL to develop cutting-edge solutions. The Impact You Will Have: Driving technological innovation in chip design and verification. Enhancing the performance and quality of synthesis tools used globally. Solving complex logic interference problems to improve design accuracy. Contributing to the development of high-performance silicon chips and software content. Collaborating with cross-functional teams to achieve project milestones. Pioneering new software architectures that set industry standards. What You'll Need: Strong hands-on experience in C/C++ based software development. Deep understanding of design patterns, data structures, algorithms, and programming concepts. Familiarity with multi-threaded and distributed code development. Knowledge of ASIC design flow and EDA tools and methodologies. Proficiency in Verilog, SystemVerilog, and VHDL HDL.

An experienced and passionate ASIC Digital Verification Engineer with a deep understanding of RTL-based IP cores and complex protocols You have over 12 years of experience in functional verification and are adept at making architectural decisions for test bench designs You are proficient in SystemVerilog (SV) and Universal Verification Methodology (UVM), and you have a proven track record of implementing coverage-driven methodologies You bring a wealth of knowledge in protocols such as DDR, PCIe, AMBA, and more Your technical expertise is matched by your strong communication skills, ability to work independently, and your innovative problem-solving capabilities Your experience may also include familiarity with functional safety standards such as ISO26262 and FMEDA What Youll Be Doing: Making architectural decisions on test bench design Writing verification plans and specifications Implementing test bench infrastructure and writing test cases Implementing a coverage-driven methodology Leading technical aspects of verification projects Collaborating with international teams of architects, designers, and verification engineers The Impact You Will Have: Enhancing the robustness and reliability of IP cores used in critical applications Driving innovation in verification methodologies and tools Ensuring high-quality deliverables through rigorous verification processes Improving productivity, performance, and throughput of verification solutions Contributing to the success of Synopsys customers in industries such as AI, automotive, and server farms Mentoring and guiding junior engineers in the verification domain What Youll Need: Knowledge of protocols such as DDR, PCIe, AMBA (AXI, CHI), SD/eMMC, Ethernet, USB, MIPI Hands-on experience with UVM/VMM/OVM, test planning, and coverage closure Proficiency in SystemVerilog and UVM, object-oriented coding, and verification Experience with scripting languages like C/C++, TCL, Perl, Python Experience with functional safety standards such as ISO26262 and FMEDA (preferred) Who You Are: Independent and precise in your work Innovative and proactive in problem-solving Excellent communicator and team player Detail-oriented with a strong analytical mindset Eager to learn and grow within a technical role The Team Youll Be A Part Of: You will join the Solutions Group at our Bangalore Design Center, India This team is dedicated to developing functional verification solutions for IP cores used in various end-customer applications You will work closely with architects, designers, and verification engineers across multiple international sites, fostering a collaborative and innovative environment

You will be implementing the industry's leading edge graphics processor, specific areas include 2D and 3D graphics, streaming processor, high speed IO interface and bus protocols. In this position, the designer will be responsible for architecture and micro-architecture design of the ASIC, RTL design and synthesis, logic and timing verification. The successful candidate for this position will specify and design digital blocks in our Multimedia Graphics team that will be integrated into a broad range of devices. All Qualcomm employees are expected to actively support diversity on their teams, and in the Company. Minimum Qualifications Bachelor's degree in Science, Engineering, or related field Previous experience in designing GPU or CPU cores and ASICs for Multimedia and Graphics applications in deep sub-micron CMOS processes for volume production Experience with Verilog/VHDL design, Synopsys synthesis, static timing analysis, formal verification, low power design, test plan development, coverage-based design verification, and/or design-for-test (DFT) Experience with Computer Architecture, Computer Arithmetic, C/C++ programming languages is desiredExposure to DX912 level graphics HW development is big plus Good communication skill and desire to work as a team player Required: Bachelor's degree in Computer Science, Electrical Engineering, Information Systems, or related field.Preferred: Master's degree in Computer Science, Electrical Engineering, Information Systems, or related field. ASIC, hardware, design, GPU, OpenGL, DirectX, RTL, Verilog, System Verilog Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Role: Hardware Platform Engineer

Ownership of a piece of the test bench Planning & execution of feature additions and mode re-enablement on particular variants Bug fixes Debug of regression signatures Developing/Deploying new tools for performance validation Performance monitor and profiler development and deployment Workload specific simulations on the emulator Following skillset is required: Strong Python, C++ skills Reading Specs and developing test plans Monitors, scoreboards, sequencers, and sequences, that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved Candidates should be comfortable checking our builds, navigating big test benches, analyzing coverage, and adding or enabling extra debug, Must be willing to dig into fail and understand what is happening 6 months - 1 Year of industry experiences in the following areas: - Basic of digital design concepts, fifo etc Basic understanding of DDR is a plus Understanding of interconnect protocols like AHB/AXI/ACE/ACE-Lite Understanding of multi-core ARMv8 CPU architecture, coherency protocols and virtualization Minimum requirement is Bachelor of Engineering however preferred is Masters of Engineering in Computer Science or Computer Engineering Candidate must possess right analytical skills, debug oriented mindset and must be open to discuss , deep dive, collate and present the design and environment understanding . Minimum Qualifications: Associates degree in Computer Science, Electrical/Electronic Engineering, Engineering, or related field.

Job Information Job Opening ID ZR_167_JOB Industry Semiconductor Date Opened 08/22/2025 Job Type Full time Work Experience 12+ Years City Bangalore / Hyderabad State/Province Karnataka / Telangana Country India Zip/Postal Code 560078 Job Description ASIC Verification Engineer – PCIe Expert (12+ years) Location: Bangalore / Hyderabad We are looking for an experienced ASIC Verification Engineer (12+ years) with a deep understanding and expertise of PCIe interface protocols (Gen1/2/3/4/5/6) . The ideal candidate thrives in dynamic environments where strong in SystemVerilog (SV) and UVM (Universal Verification Methodology) is highly valued. Key Responsibilities / What you’ll do: Deliver high-quality RTL and simulation models with strong focus on accuracy and efficiency. Develop, review, and execute verification plans and test environments at IP and/or SoC level. Apply a proactive, problem-solving mindset to complex design and verification challenges. Lead verification teams, mentor junior engineers, and interact and collaborate directly with customers to ensure seamless execution. Preferred Experience / What We’re Looking For: 12+ years of ASIC verification experience . Strong hands-on expertise in PCIe verification (IP or SoC level). Proven experience with UVM-based test benches and complex verification environments. Ability to work in collaborative, fast-paced environments with a commitment to quality, innovation and technical leadership .

Principal Staff Verification Engineer (VLSI Verification + AV +AI Expertise) Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. Thu, Aug 21 at 4:49 PM Job Description – Staff Verification Engineer (VLSI Verification + AV +AI Expertise) Position: Staff Verification Engineer – VLSI Verification Lead Location: Hyderabad Experience: 12+ years in Functional Verification Key Protocol Experience: MIPI DSI, DisplayPort, HDMI Role Overview We are seeking a highly skilled Staff Verification Engineer with strong expertise in VLSI functional verification and a good understanding of AI model deployment for Audio/Video applications. The candidate will lead verification efforts for complex SoCs/IPs, while also collaborating with cross-functional teams on next-generation multimedia and AI-driven system use cases. Requirements Experience: 12+ years in functional verification; minimum 5+ years in Multimedia (Display, Camera, Video, Graphics) domain . Domain Expertise: Strong knowledge in Display (Pixel processing, composition, compression, MIPI DSI, DisplayPort, HDMI) and Bus/Interconnect (AHB, AXI). Multimedia technologies: Audio/Video codecs, Image Processing, SoC system use cases (Display, Camera, Video, Graphics). Good understanding of DSP, codecs (audio/video), and real-time streaming pipelines. AI accelerators – architecture understanding, verification, and deployment experience across NPUs, GPUs, and custom AI engines. SoC system-level verification with embedded RISC/DSP processors. AI/ML Skills: Experience with AI models (ex. CNN ) and statistical modeling techniques. Exposure to audio frameworks, audio solutions, and embedded platforms. Hands-on in multimedia use cases verification and system-level scenarios. Strong exposure to MIPI DSI-2, CSI-2, MIPI D-PHY, C-PHY. Verification Expertise: Proven expertise in developing/maintaining SystemVerilog/UVM-based testbenches, UVCs, sequences, checkers, coverage models. Strong understanding of OOP concepts in verification. HVL: SystemVerilog (UVM), SystemC (preferred). HDL: Verilog, SystemVerilog. Leadership & Collaboration: Mentor and guide junior verification engineers; drive closure for IP and SoC-level deliverables. Strong written and verbal communication skills; ability to convey complex technical concepts. Proven ability to plan, prioritize, and execute effectively. Debugging & Architecture Knowledge: Excellent debug skills across SoC architecture, VIP integration, and verification flows. Responsibilities AI & Multimedia (AV) Responsibilities Develop, optimize, and deploy AI models for audio and video applications, with strong focus on inference efficiency and performance optimization across NPUs, GPUs, and CPUs. Perform model evaluation, quantization, and compression to enable fast and robust inference on embedded hardware. Collaborate with cross-functional R&D, systems, and integration teams for system use case verification and commercialization support. Evaluate system performance, debug, and optimize for robustness and efficiency. Participate in industry benchmarking and trend analysis; introduce state-of-the-art architectural and technical innovations. ASIC / SoC Verification Responsibilities Lead and contribute to feature, core, and subsystem verification during ASIC design and development phases through RTL and Gate-Level simulations. Collaborate with the design team to define verification requirements, ensuring functional, performance, and power correctness. Develop and execute comprehensive test plans and drive verification closure. Create and maintain SystemVerilog/UVM testbenches, assertions, and functional coverage models. Implement and enhance automation flows to improve verification efficiency. Participate in debug activities throughout the development cycle. Apply ASIC expertise to define, model, optimize, verify, and validate IP (block/SoC) development for high-performance, low-power products. Collaborate with software and hardware architecture teams to develop strategies meeting system-level requirements. Evaluate complete design flows from RTL through synthesis, place-and-route, timing, and power usage. Write detailed technical documentation for verification methodologies, flows, and deliverables. Contact: Uday Bhaskar Mulya Technologies "Mining the Knowledge Community" Email id : muday_bhaskar@yahoo.com

Principal Staff Verification Engineer (VLSI Verification + AV +AI Expertise) Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. Thu, Aug 21 at 4:49 PM Job Description – Staff Verification Engineer (VLSI Verification + AV +AI Expertise) Position: Staff Verification Engineer – VLSI Verification Lead Location: Hyderabad Experience: 12+ years in Functional Verification Key Protocol Experience: MIPI DSI, DisplayPort, HDMI Role Overview We are seeking a highly skilled Staff Verification Engineer with strong expertise in VLSI functional verification and a good understanding of AI model deployment for Audio/Video applications. The candidate will lead verification efforts for complex SoCs/IPs, while also collaborating with cross-functional teams on next-generation multimedia and AI-driven system use cases. Requirements Experience: 12+ years in functional verification; minimum 5+ years in Multimedia (Display, Camera, Video, Graphics) domain . Domain Expertise: Strong knowledge in Display (Pixel processing, composition, compression, MIPI DSI, DisplayPort, HDMI) and Bus/Interconnect (AHB, AXI). Multimedia technologies: Audio/Video codecs, Image Processing, SoC system use cases (Display, Camera, Video, Graphics). Good understanding of DSP, codecs (audio/video), and real-time streaming pipelines. AI accelerators – architecture understanding, verification, and deployment experience across NPUs, GPUs, and custom AI engines. SoC system-level verification with embedded RISC/DSP processors. AI/ML Skills: Experience with AI models (ex. CNN ) and statistical modeling techniques. Exposure to audio frameworks, audio solutions, and embedded platforms. Hands-on in multimedia use cases verification and system-level scenarios. Strong exposure to MIPI DSI-2, CSI-2, MIPI D-PHY, C-PHY. Verification Expertise: Proven expertise in developing/maintaining SystemVerilog/UVM-based testbenches, UVCs, sequences, checkers, coverage models. Strong understanding of OOP concepts in verification. HVL: SystemVerilog (UVM), SystemC (preferred). HDL: Verilog, SystemVerilog. Leadership & Collaboration: Mentor and guide junior verification engineers; drive closure for IP and SoC-level deliverables. Strong written and verbal communication skills; ability to convey complex technical concepts. Proven ability to plan, prioritize, and execute effectively. Debugging & Architecture Knowledge: Excellent debug skills across SoC architecture, VIP integration, and verification flows. Responsibilities AI & Multimedia (AV) Responsibilities Develop, optimize, and deploy AI models for audio and video applications, with strong focus on inference efficiency and performance optimization across NPUs, GPUs, and CPUs. Perform model evaluation, quantization, and compression to enable fast and robust inference on embedded hardware. Collaborate with cross-functional R&D, systems, and integration teams for system use case verification and commercialization support. Evaluate system performance, debug, and optimize for robustness and efficiency. Participate in industry benchmarking and trend analysis; introduce state-of-the-art architectural and technical innovations. ASIC / SoC Verification Responsibilities Lead and contribute to feature, core, and subsystem verification during ASIC design and development phases through RTL and Gate-Level simulations. Collaborate with the design team to define verification requirements, ensuring functional, performance, and power correctness. Develop and execute comprehensive test plans and drive verification closure. Create and maintain SystemVerilog/UVM testbenches, assertions, and functional coverage models. Implement and enhance automation flows to improve verification efficiency. Participate in debug activities throughout the development cycle. Apply ASIC expertise to define, model, optimize, verify, and validate IP (block/SoC) development for high-performance, low-power products. Collaborate with software and hardware architecture teams to develop strategies meeting system-level requirements. Evaluate complete design flows from RTL through synthesis, place-and-route, timing, and power usage. Write detailed technical documentation for verification methodologies, flows, and deliverables. Contact: Uday Bhaskar Mulya Technologies "Mining the Knowledge Community" Email id : muday_bhaskar@yahoo.com