Senior Staff Physical Design Engineer

Senior Staff Physical Design Engineer (India)/ Bangalore (Hybrid ) / Hyderabad (Hybrid )

Company Background

We are one among 49 US AI startups that have raised $100M or more in 2024

We are on a mission to revolutionize AI compute systems and infrastructure at scale through the development of superior-scaling networking silicon and software which we call the Accelerated Compute Fabric. Founded and led by an executive team assembled from first-class semiconductor and distributed systems/software companies throughout the industry, sets themselves apart from other startups with a very strong engineering pedigree, a proven track record of delivering, deploying and scaling products in data center production environments, and significant investor support for our ambitious journey! Together, with their differentiated approach to solving the I/O bottlenecks in distributed AI and accelerated compute clusters, We are unleashing the revolution in next-gen computing fabrics.

Summary

Join an ambitious, experienced team of silicon and distributed systems experts as a design verification engineer. You have the opportunity to build a groundbreaking new category of product that revolutionizes the performance and scalability of next-generation distributed computing systems, and to help solve key infrastructure challenges facing our customers.

We are looking for talented, motivated candidates with experience designing and verifying large-scale networking and computing chips, and who are looking to grow in a fast paced, dynamic startup environment. We seek experienced verification engineers who can contribute across the full lifecycle of complex chip development, from microarchitecture definition to DV infrastructure and test development, to post-silicon testing.

Roles and Responsibilities

• Build and support the CAD tool flow for physical implementation in a cloud-first development environment.

• Work with architects and microarchitects on the chip-level floorplan and block partitioning. Evaluate tradeoffs in functional partitioning, block size, and interface complexity with other stakeholders.

• Define and construct the major physical structures, including the clock and reset architecture, the power delivery network, and interconnect topologies.

• Execute on block-level, cluster-level, and top-level physical implementation, from synthesis, floorplan and power plan, through P+R, through timing closure, physical verification, and tapeout.

• Interface with foundry and library partners on 3rd party IP and process technology issues, including updates to device models, IP integration requirements, and pre-tapeout signoff.

Skills/Qualifications:

• Proven industry experience and successful track record in the physical implementation of large, high-performance network switching/routing fabrics (Ethernet, Infiniband, HPC), Network Interface Controllers, Smart-NICs, CPUs, or GPUs in the latest silicon process nodes.

• Deep experience with the latest CAD tools through the entire physical design workflow, e.g., Cadence Genus and Innovus, Synopsys ICC2/FusionCompiler, Tempus, PrimeTime SI, PrimeTime PX, StarRC, ICV, Calibre.

• Strong familiarity with various analysis tools such as Redhawk, Voltus.

• Experience with circuit analysis using HSPICE is a plus.

• Expert knowledge of SystemVerilog, as well as Perl, Python or other scripting languages.

• Minimum BSEE/CE/MSEE/CE with 8-12 + years experience.

• Proven track record of execution on products which have shipped in high-volume.

Contact:

Sumit S. B.

Mulya Technologies

sumit@mulyatech.com

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