526 Systemverilog Jobs - Page 7

Hi Folks ACL Digital is Hiring! Experience: 4 - 5+ Years Location: Bangalore / Hyderabad Looking: Immediate to 20 days Hiring | RTL Design Engineer Strong experience in RTL Design using Verilog/System Verilog Exposure to complex SoC/ASIC design and integration Hands-on with synthesis, Lint, CDC preferred Share resume at himabindu.jeevarathnam@acldigital.com #RTLEngineer #ACLdigital #VLSIJobs #ASICDesign #Verilog #SystemVerilog #SoC Thanks, K Himabindu

As a Verification Engineer at Google, you will play a crucial role in ensuring the functionality and performance of Google's custom silicon solutions. You will be responsible for verifying digital systems, including infrastructure IP, interconnects, caches, memory management, and system services. Your expertise will be instrumental in shaping the next generation of hardware experiences, delivering unmatched performance, efficiency, and integration. Your responsibilities will include planning and executing the verification of configurable Infrastructure IPs, interconnects, and memory subsystems. You will develop and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM). Additionally, you will create cross-language tools and scalable verification methodologies to ensure comprehensive testing coverage. To excel in this role, you should have a Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience. You should possess experience in verifying digital systems using standard IP components/interconnects, such as microprocessor cores and hierarchical memory subsystems. Proficiency in Design Verification Test, SystemVerilog, Verilog, Computer Architecture, System On a Chip, C, C++, and Python is required. Experience in creating and using verification components and environments in standard verification methodology, scripting languages, and software development frameworks is essential. Preferred qualifications for this position include a Master's degree or PhD in Electrical Engineering or Computer Science, along with 3 years of experience in areas such as Caches Hierarchies, Coherency, Memory Consistency Models, DDR/LPDDR, PCIe, Packet Processors, Security, or Clock and Power Controllers. Experience with building verification methodologies spanning simulation, emulation, and Field Programmable Gate Array (FPGA) prototypes is advantageous. Knowledge of Interconnect Protocols (e.g., AHB, AXI, ACE, CHI, CCIX, CXL), performance verification of SOCs, pre-Silicon analysis, and post-Silicon correlation is also beneficial. Join our team at Google and be part of the innovation that drives the future of direct-to-consumer products. Your contributions will have a global impact, shaping products loved by millions worldwide. Embrace the opportunity to work on the verification of Google's System on a Chip (SOC) offerings, collaborating with hardware architects and design engineers to deliver cutting-edge hardware experiences. Your role will involve developing performance Virtual IP address (VIPs) for supported protocols, deploying verification stacks across diverse IPs, and building generalized system topology abstractions. Together, we will develop methodologies and tools to tackle complex challenges and advance technology for the betterment of society.,

Meta is hiring ASIC Formal Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Formal Verification to build IP and System On Chip (SoC) for data center applications. As a Formal Verification Engineer, you will be part of a team working with the best in the industry, focused on developing innovative ASIC solutions for Facebook’s data center applications. You will be developing comprehensive formal testplans and be responsible for complete formal verification sign-off of single or multiple complex blocks. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success. ASIC Engineer, Formal Verification Responsibilities: Propose, implement and promote the Formal Verification Methodology to be used across the group, both at the top level and at the block level Work with Architecture and Design teams to come up with Formal Verification specification and implementation Define Formal Verification scope, create Formal environment and close coverage with targeted Formal Verification Techniques at IP, Subsystem and SoC level Build reusable/scalable environments for Formal Verification and deploying tools Evaluate and recommend EDA solutions for Formal Verification Provide training for internal teams and mentoring engineers related to Formal Verification Technology Minimum Qualifications: Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 7+ years of experience in Formal Verification Experience with Formal Verification applications including Datapath, sequential equivalence, Xprop, Clock Gating, connectivity etc. Experience with Formal Verification methodologies, complexity reduction techniques and abstraction techniques Experience using analytical skills to craft novel solutions to tackle industry-level complex designs Demonstrated experience with effective collaboration with cross functional teams Fluency in hardware description languages, such as SystemVerilog and SVA Proficiency in scripting languages such as Python, Perl, or Tcl Experience with JasperGold or VC-Formal Preferred Qualifications: Experience to quickly understand and interpret specifications and extract design behaviors/properties Experience in formal property verification of complex compute blocks like DSP, CPU, GPU or HW accelerators Experience with complex SoCs Formal verification experience in clock domain crossing, IP-XACT based register verification and low power Experience with development of fully automated flows from specification to fully verified designs Experience with simulators and waveform debugging tools About Meta: Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics. Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.

IPrincipal P/RTL Design Engineer for ARM CMN Fabric and Neoverse Hyderabad / Bangalore Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore Principal IP/RTL Design Engineer for ARM CMN Fabric and Neoverse Position Overview Seeking an IP/RTL Design Engineer with 10+ years of experience to design IP/RTL for ARM Neoverse-based SoCs, focusing on CMN fabric, using Socrates for configuration, targeting AI/HPC datacenter applications. Key Responsibilities Design IP blocks for ARM Neoverse SoCs, integrating CMN fabric (e.g., CMN-700/S3) for cache coherence and interconnect. Develop Verilog/SystemVerilog RTL for high-performance, low-latency designs. Configure CMN topologies using Arm Socrates for optimized performance and scalability. Implement protocols like AMBA CHI, ACE, CXL, PCIe for coherent interconnects. Optimize designs for bandwidth, latency, and power in AI/HPC workloads. Support synthesis, timing closure, and FPGA prototyping and Design Verification team Document microarchitecture and design specifications. Required Qualifications Education: BS/MS/PhD in Electronics/Computer Engineering. Experience: 10+ years in ASIC/FPGA IP/RTL design, 5+ years with ARM Neoverse and CMN fabrics (e.g., CMN-600/700/S3). Skills: Expert in Verilog/SystemVerilog RTL design. Deep knowledge of ARM Neoverse (V1/V3/N2/N3) and CMN interconnects. Deep understanding in system architecture, coherence and cache Experience with Arm Socrates for CMN configuration. Proficiency in AMBA CHI, CXL, PCIe, or CCIX protocols. Familiarity with synthesis and timing tools (e.g., Synopsys Design Compiler). Experience with AI/HPC or datacenter SoC design. Knowledge of DDR5, HBM3, or chiplet-based architectures. Familiarity with UALink or Ultra Ethernet. Strong problem-solving and collaboration skills. What is in it for you? Pure play product work environment Chance to work with a tightly knit group of exceptional engineers who come from the top companies of the Semiconductor world Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. A meritocracy first work place where each peer is a star A chance to be a part of industry shaping product in entirety (not bits and pieces) from initial stages A chance to work at a startup which already has customers and investor lined up for their product pipeline (We do not have a marketing/sales team, because we do not need them). A chance to learn from industry veterans who have already launched multiple Billion Dollar Semiconductor firms over the last 3 decades. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Principal IP/RTL Design Engineer for TPU Hyderabad / Bangalore Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore IP/RTL Design Engineer for TPU Position Overview Seeking an IP/RTL Design Engineer with 5+ years of experience to design IP/RTL for TPUs, focusing on high-performance matrix multiplication, low-latency interconnects, and power-efficient AI acceleration. Key Responsibilities Design IP blocks for TPU cores, including systolic arrays, vector units, and memory subsystems. Develop Verilog/SystemVerilog RTL for performance, timing, and area optimization. Implement high-speed interconnects (e.g., AXI, NoC) for TPU data pipelines. Optimize designs for high throughput, low latency, and power efficiency in AI workloads. Integrate LPDDR6, HBM3, DDR5, or chiplet-based memory interfaces. Support synthesis, timing closure, and FPGA prototyping and Design Verification team Document microarchitecture and design specifications. Required Qualifications Education: BS/MS in Electrical/Computer Engineering. Experience: 10+ years in ASIC/FPGA IP/RTL design, with 3+ years in AI accelerators or TPU-like architectures. Skills: Proficient in Verilog/SystemVerilog RTL design. Knowledge of TPU architectures, systolic arrays, or matrix multiplication units. Experience with AXI, NoC, or similar interconnect protocols. Familiarity with LPDDR6, HBM3, DDR5, or high-bandwidth memory interfaces. Proficiency with synthesis and timing tools (e.g., Synopsys Design Compiler). Strong problem-solving and teamwork skills. Preferred Qualifications Experience with AI/ML workloads or datacenter TPU designs and GPU architectures Knowledge of CXL, PCIe, UALink, or Ultra Ethernet. Familiarity with power optimization for high-performance chips. What is in it for you? Pure play product work environment Chance to work with a tightly knit group of exceptional engineers who come from the top companies of the Semiconductor world Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. A meritocracy first work place where each peer is a star A chance to be a part of industry shaping product in entirety (not bits and pieces) from initial stages A chance to work at a startup which already has customers and investor lined up for their product pipeline (We do not have a marketing/sales team, because we do not need them). A chance to learn from industry veterans who have already launched multiple Billion Dollar Semiconductor firms over the last 3 decades. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Principal IP/RTL Design Engineer for Ethernet Switch Hyderabad / Bangalore Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore Position Overview IP/RTL Design Engineer for Ethernet Switch Position Overview We are seeking an experienced IP/RTL Design Engineer with over 10 years of experience to join our team in designing and developing intellectual property (IP) and RTL for Ethernet switches tailored for AI datacenter backend networks. The ideal candidate will have a strong background in digital design, ASIC/FPGA development, Ethernet protocols, and experience with high-performance interconnect protocols such as InfiniBand, NVLink, Infinity Fabric, with a focus on delivering high-performance, low-latency solutions for large-scale AI workloads. Key Responsibilities Design and optimize IP blocks (MAC, PCS, packet processors) for Ethernet switches. Develop synthesizable RTL (Verilog/SystemVerilog) meeting performance and timing goals. Optimize designs for low latency, high throughput, and power efficiency. Implement Ethernet protocols (IEEE 802.3, 100G/400G/800G), ECMP, and congestion control. Apply knowledge of InfiniBand, NVLink, or similar protocols for feature implementation. Use P4 or related languages for programmable packet processing. Collaborate with teams for synthesis, timing closure, and IP integration. Document designs and stay updated on AI networking trends. Required Qualifications Education: BS/MS/PhD in Electrical or Computer Engineering. Technical Skills: Proficient in Verilog/SystemVerilog for design. Knowledge of Ethernet (IEEE 802.3, 100G/400G/800G), ECMP, and congestion control. Experience with InfiniBand, NVLink, or similar protocols. Proficiency in P4 or programmable data plane languages. Knowledge of UALink, Ultra Ethernet, or RDMA/RoCE. Familiarity with power optimization or SDN. Familiarity with synthesis (e.g., Synopsys Design Compiler) and timing tools. Soft Skills: Strong problem-solving, communication, and teamwork skills. What is in it for you? Pure play product work environment Chance to work with a tightly knit group of exceptional engineers who come from the top companies of the Semiconductor world Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. A meritocracy first work place where each peer is a star A chance to be a part of industry shaping product in entirety (not bits and pieces) from initial stages A chance to work at a startup which already has customers and investor lined up for their product pipeline (We do not have a marketing/sales team, because we do not need them). A chance to learn from industry veterans who have already launched multiple Billion Dollar Semiconductor firms over the last 3 decades. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: SE NIOR SILICON DESIGN ENGINEER KEY RESPONSIBILITIES: Develop, enhance, and maintain SystemC/TLM2 models for memory controllers, peripherals, and interconnects, ensuring they accurately simulate the behavior and performance characteristics of the hardware Collaborate with cross teams to integrate models into AMD tools used for system-level designs, ensuring proper functionality and performance Identify bottlenecks and performance issues within models and work to optimize their performance to meet design specifications Develop and execute testbenches to validate the functionality and correctness of models, as well as participate in system-level testing and debugging Create clear and comprehensive documentation for models, including usage guidelines and design specifications. Digital design and experience with RTL design in Verilog/SystemVerilog, Knowledge of system-level architecture including buses like AXI/AHB, bridges is a plus Version control systems such as Perforce, ICManage or Git PREFERRED EXPERIENCE: B.E/M.E/M.Tech or B.S/M.S in EE/CE with 5+ years of relevant experience in SystemC modelling Proven experience in SystemC and TLM2 modeling Strong understanding of memory controller architectures, including DDR, LPDDR, and other relevant standards Proficiency in C/C++ programming UVM Verification Experience Strong verbal and written communication skills Should have experience working in geographically dispersed team and should be a strong team player ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR5 Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

About Us: Silcosys Solutions Private Limited is a pioneer in semiconductor innovation, committed to delivering cutting-edge analog design solutions that power the future of technology. If you are eager to work on impactful projects and advance your expertise, we invite you to join our dynamic team. Job Description: As an RTL Design Engineer, you will be responsible for designing and implementing high-quality RTL code for complex digital blocks and subsystems. You will collaborate with architects, verification, and physical design teams to create designs that meet functional, performance, and power requirements. Responsibilities: Develop RTL designs for digital IPs, subsystems, and SoCs based on architectural specifications. Collaborate with architects and system engineers to translate high-level requirements into detailed micro-architecture. Perform design optimizations for area, power, and performance. Conduct design reviews and ensure compliance with coding standards and best practices. Work closely with verification teams to develop test plans and ensure 100% functional coverage. Debug and resolve design and integration issues during simulation and post-silicon validation. Participate in timing analysis and closure in collaboration with the physical design team. Document design specifications, test cases, and user guides for IP and SoC designs. Requirements: Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field. 2-10 years of experience in RTL design and implementation for VLSI systems. Strong expertise in Verilog, SystemVerilog, and RTL design methodologies. Solid understanding of digital design concepts such as pipelining, clock domain crossing, and low-power design techniques. Experience with EDA tools like Synopsys Design Compiler, Cadence Genus, or equivalent. Proficiency in scripting languages (Python, Perl, TCL) for design automation. Familiarity with SoC interfaces and protocols like AXI, AHB, PCIe, USB, or DDR. Experience in static timing analysis (STA) and timing closure workflows. Strong problem-solving skills and the ability to debug complex design issues. Excellent communication and collaboration skills to work effectively in a team environment. Preferred Qualifications: Experience with low-power design and multi-clock domain systems. Knowledge of advanced process nodes (e.g., 7nm, 5nm, or below) and FinFET technologies. Exposure to formal verification methodologies. Experience in hardware-software co-design and FPGA prototyping. Familiarity with machine learning or AI-based RTL optimizations. Why Join Us Work on groundbreaking projects in VLSI design and technology. Collaborate with a team of industry experts in a supportive and innovative environment. Opportunities for career growth and continuous learning. Competitive salary and benefits. How to Apply: If this role excites you, submit your updated resume at info@silcosys.com and any relevant project portfolios today. Join Silcosys Solutions Private Limited and shape the future of analog design!,

Siemens EDA is a global technology leader in Electronic Design Automation software, enabling companies worldwide to develop innovative electronic products efficiently. Customers utilize our tools to advance technology and physics boundaries for superior products in chip, board, and system design. Join the Questa Simulation Product core R&D team based in Noida, working on various simulation verticals with a dynamic and motivated group. The role may involve travel to different locations, offering opportunities to collaborate on impactful projects globally. As a software engineer in the QuestaSim R&D team, you will be responsible for core algorithmic advancements, software design, and architecture. Collaborate with senior software engineers to enhance new components, algorithms, and engines while maintaining production-quality code. Self-motivation, goal-setting, and consistent work in a dynamic environment are keys to success in this role. Qualifications: - B.Tech or M.Tech in CSE, EE, or ECE from a reputable institution with 12+ years of experience. - Proficiency in C/C++, algorithms, data structures, compiler concepts, and optimizations. - Knowledge of UNIX/Linux platforms. - Strong problem-solving and analytical skills. - Ability to work independently and lead project teams. Desirable Skills: - Understanding of digital electronics concepts. - Familiarity with ML, AI algorithms, Verilog, SystemVerilog, VHDL, parallel algorithms, and job distribution techniques. - Experience in simulation or formal verification methodologies. Join Siemens, a global team of over 377,000 minds shaping the future across 200+ countries. We value diversity and encourage applications reflecting the communities we serve. Employment decisions are based on qualifications, merit, and business requirements. Bring your creativity and curiosity to help build tomorrow's innovations. Transform the everyday with Siemens EDA.,

As a Siemens EDA ambassador, you will play a crucial role in the fast-evolving electronics industry by empowering customers to introduce groundbreaking innovations to the market swiftly and attain leadership in their respective sectors. Siemens EDA is committed to providing a comprehensive range of electronic design automation (EDA) software, hardware, and services on a global scale to achieve this goal. Your primary responsibilities will involve spearheading the design, development, and implementation of software solutions for both internal and external products. It is essential to ensure that the delivered solutions not only meet but exceed customer expectations while maintaining the highest quality standards. Your role will be instrumental in ensuring the functional excellence of released products across various platforms, addressing intricate challenges proactively. Additionally, you will be accountable for devising and executing software designs that span multiple product domains, collaborating seamlessly with cross-functional teams to enhance efficiency, boost performance, and elevate our solutions. To qualify for this role, we are seeking individuals with a B.E./B.Tech./M.Tech. degree in Computer Science, Electrical Engineering, Electronics & Communication, Instrumentation & Control, or related fields. You should have 3-5 years of experience in software development, with a specific focus on FPGA synthesis solutions. Proficiency in digital design fundamentals, C/C++, and Object-Oriented Programming (OOP) is essential. A strong aptitude for algorithm analysis, development, and optimization of data structures is crucial, coupled with a commitment to continuous improvement through open and constructive feedback. Having familiarity with synthesis, simulation, and verification methodologies would be advantageous for this role. Moreover, a basic understanding of at least one Hardware Description Language (HDL) such as Verilog, SystemVerilog, VHDL, or SystemC is highly beneficial. This position is based in Noida, offering you the opportunity to collaborate with diverse teams, contribute to shaping the future, driving innovation, and delivering cutting-edge solutions. Siemens is a global organization comprising over 377,000 talented individuals working across 200 countries. We are dedicated to promoting diversity and equality in the workplace, and we value applications that reflect the communities in which we operate. Employment decisions at Siemens are merit-based and driven by qualifications and business requirements. Join us with your curiosity and creativity to help shape a better tomorrow! In return, we provide a competitive basic salary, bonus scheme, generous holiday allowance, pension, and private healthcare benefits. If you are passionate about transforming the ordinary into extraordinary and want to be part of a dynamic team committed to innovation, then this role at Siemens EDA is the perfect opportunity for you.,

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SENIOR SILICON DESIGN ENGINEER KEY RESPONSIBILITIES: Develop, enhance, and maintain SystemC/TLM2 models for memory controllers, peripherals, and interconnects, ensuring they accurately simulate the behavior and performance characteristics of the hardware Collaborate with cross teams to integrate models into AMD tools used for system-level designs, ensuring proper functionality and performance Identify bottlenecks and performance issues within models and work to optimize their performance to meet design specifications Develop and execute testbenches to validate the functionality and correctness of models, as well as participate in system-level testing and debugging Create clear and comprehensive documentation for models, including usage guidelines and design specifications. Digital design and experience with RTL design in Verilog/SystemVerilog, Knowledge of system-level architecture including buses like AXI/AHB, bridges is a plus Version control systems such as Perforce, ICManage or Git PREFERRED EXPERIENCE: B.E/M.E/M.Tech or B.S/M.S in EE/CE with 5+ years of relevant experience in SystemC modelling Proven experience in SystemC and TLM2 modeling Strong understanding of memory controller architectures, including DDR, LPDDR, and other relevant standards Proficiency in C/C++ programming UVM Verification Experience Strong verbal and written communication skills Should have experience working in geographically dispersed team and should be a strong team player ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

We are actively hiring multiple Design Verification (DV) Engineers for Bangalore (hybrid model). If youre looking for a new challenge and can join quickly, youll be among our top-priority candidates! Open Positions : 1. DV Engineer GLS / UVM / SystemVerilog / CDC Experience : 3–8 years Skills : Gate-Level Simulations, UVM testbench development, CDC verification, timing-aware verification 2. DV Engineer – PCIe / DDR / UVM / SV Experience : 4–18 years Skills : Protocol-level verification, PCIe or DDR, UVM, SystemVerilog 3. DV Engineer – UVM / SystemVerilog Experience : 5–10 years Skills : Testbench architecture, functional verification, scalable UVM environments

Job Description : We are looking for a VLSI MBIST Engineer with strong expertise in Memory Built-In Self-Test (MBIST) methodologies for ASIC/SoC designs. The ideal candidate should have hands-on experience using Synopsys SMS tool and a solid understanding of MBIST test development, pattern generation, and fault simulation. Key Responsibilities : Develop and implement MBIST algorithms and test patterns for embedded memories (SRAM, DRAM, ROM, CAM) Use Synopsys SMS tool for MBIST pattern generation and validation Perform fault modeling, fault simulation, and fault coverage analysis Integrate MBIST macros into SoC designs in collaboration with RTL and physical design teams Debug MBIST issues in pre- and post-silicon stages Document MBIST flows, generate test reports, and provide support for DFT reviews Stay updated on industry trends and best practices in MBIST and memory testing Required Skills : B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, VLSI, or related fields 4+ years of experience in MBIST implementation and validation Strong experience with Synopsys SMS tool Proficiency in scripting languages like TCL, Perl, or Python Good knowledge of Verilog/SystemVerilog and digital design fundamentals Familiarity with simulation tools like VCS, ModelSim Preferred Skills : Experience with DFT tools such as Tessent Knowledge of ATPG, JTAG (IEEE 1149.1), and IEEE 1500 standards Exposure to silicon bring-up and failure analysis

Key Responsibilities: Develop and execute comprehensive verification plans for SoC and NoC systems Design and maintain test benches using SystemVerilog and UVM Perform functional, performance, and low-power verification Debug and resolve design/verification issues independently Work with high-speed protocols such as AXI, CHI, PCIe, Ethernet, CXL, and UCIe Ensure thorough coverage and compliance with design specifications Collaborate with cross-functional teams including RTL, DFT, and architecture Required Skills: 7+ years of hands-on experience in SoC/NoC verification Strong expertise in System Verilog, UVM, and scripting (Python/Perl/TCL) Experience with simulation tools like VCS, Questa, or Incisive Solid understanding of interconnect protocols: AXI, CHI, PCIe, Ethernet, etc. Familiarity with coverage analysis and debugging tools Strong analytical and problem-solving skills Preferred: Experience with CXL or UCIe protocols Exposure to formal verification or emulation tools is a plus

Job Description We are seeking a Senior Staff Verification Engineer to lead and contribute to the functional verification of complex SoC and IP designs for next-generation AI, HPC, and data center products. The ideal candidate has extensive experience in UVM/SystemVerilog , SoC and IP-level verification, and is passionate about ensuring first-pass silicon success . This role involves defining verification strategies, developing scalable environments, and collaborating cross-functionally with architecture, design, and software teams. Experience with Virtual Modeling, SystemC, and TLM is a plus , enabling advanced verification and early system-level validation. Qualifications Required Qualifications Education & Experience B.S./M.S. in Electrical Engineering, Computer Engineering, or related field. 8+ years of experience in IP/SoC verification with a proven track record of successful silicon delivery. Technical Expertise Deep knowledge of UVM/SystemVerilog for testbench development and verification IP integration. Strong understanding of SoC architecture and protocols such as DDR5, HBM3, PCIe Gen6, CXL 3.0 , and other high-speed interfaces. Expertise in coverage-driven verification , constrained-random testing, and assertion-based verification. Proficient in debugging RTL, testbenches, and simulation failures using industry-standard tools. Tools & Languages Hands-on experience with simulation tools (VCS, Xcelium, Questa, etc.), waveform viewers, coverage tools, and automation scripting (Python, Perl, TCL). Preferred/Additional Skills Virtual Modeling and System-Level Verification Familiarity with SystemC and Transaction-Level Modeling (TLM) for virtual prototyping and early system validation. Experience developing or using virtual platforms for hardware/software co-verification is a strong plus. Emulation & Prototyping Exposure to emulation platforms (Palladium, ZeBu) and FPGA-based prototyping for system-level validation and performance analysis. Software Co-verification Experience working alongside firmware/software teams for pre-silicon software validation and early driver/OS bring-up. Low-Power and DFT Verification Knowledge of power-aware verification (UPF/CPF) and DFT validation methodologies is desirable. Additional Information Key Responsibilities Verification Planning & Execution Lead the definition, development, and execution of comprehensive verification plans at IP and SoC levels. Develop UVM/SystemVerilog-based testbenches , including stimulus generation, checkers, and monitors for advanced SoC designs. Drive coverage-driven verification processes, ensuring functional and code coverage goals are met. Cross-Functional Collaboration Collaborate with architecture, RTL design, firmware, software, and emulation teams to define verification requirements and ensure comprehensive test coverage. Participate in design and architecture reviews , providing critical feedback on functionality, testability, and performance considerations. Debug & Issue Resolution Lead debug efforts on complex SoC and IP issues through simulation, emulation, and FPGA prototypes. Perform root-cause analysis and drive issues to closure in partnership with cross-disciplinary teams. Methodology & Infrastructure Development Enhance and maintain verification methodologies , including reusable verification IP, automation scripts, and regression infrastructure. Evaluate and adopt new tools and verification technologies to improve quality and efficiency. Leadership & Mentorship Provide technical guidance and mentorship to junior verification engineers. Lead verification reviews and strategy discussions , ensuring high technical standards and best practices. Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, you can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

Job Description Job Summary We are seeking a Principal Verification Engineer to lead the functional verification of complex SoCs and IP blocks for next-generation high-performance computing (HPC), AI acceleration, and data center products. The ideal candidate will have deep experience in SoC/IP functional verification , UVM/SystemVerilog , and coverage-driven methodologies , with a strong focus on ensuring first-pass silicon success. In this leadership role, you will drive end-to-end verification strategy , collaborate cross-functionally with architecture and design teams, and influence product definition through early design engagement. Experience in Virtual Modeling, SystemC, and TLM is a strong plus , enabling advanced verification flows and early software co-development. Key Responsibilities Verification Planning & Execution Own the definition and implementation of IP and SoC-level verification plans , including test strategy, coverage goals, and schedule. Develop UVM/SystemVerilog-based testbenches for complex IP and SoC subsystems, focusing on scalability, reuse, and maintainability. Lead coverage closure activities, including functional, code, and formal coverage, to ensure comprehensive verification. Cross-Functional Collaboration Work closely with RTL designers, architects, firmware/software teams , and post-silicon validation to align on requirements and drive co-verification strategies. Participate in architecture and microarchitecture reviews , providing verification insights and influencing design for testability and verification efficiency. Debug & Root Cause Analysis Perform advanced debug and root cause analysis of complex functional issues, collaborating with cross-disciplinary teams to drive resolutions. Utilize industry-standard tools for waveform analysis, simulation debug, and emulation/prototyping platforms . Methodology & Process Improvement Define and drive best practices in verification methodology , including constrained-random testing, assertion-based verification, and coverage-driven approaches. Contribute to automation and regression flows , optimizing for quality and turnaround time. Technical Leadership & Mentorship Mentor junior verification engineers, guide technical reviews, and contribute to team development and growth. Champion a culture of technical excellence, innovation, and continuous improvement . Qualifications Required Qualifications Education & Experience B.S./M.S. in Electrical Engineering, Computer Engineering, or related discipline. 10+ years of hands-on experience in IP and/or SoC verification with a track record of successful silicon products. Technical Expertise Proven expertise in UVM/SystemVerilog for developing scalable, reusable verification environments. Strong understanding of complex SoC designs , including memory controllers (DDR5, HBM3), PCIe, CXL , and high-speed interfaces. Experience with coverage-driven verification and closure techniques (functional, code, assertion coverage). Solid background in debugging RTL issues , simulation-based testing, and interaction with emulation/FPGA prototyping teams. Verification Tools & Languages Proficient in simulation tools (VCS, Questa, Xcelium), waveform viewers , and scripting languages ( Python, Perl, TCL ) for automation. Familiarity with formal verification tools and techniques is a plus. Additional Information Preferred/Additional Skills Virtual Modeling and System-Level Verification Experience with SystemC and Transaction-Level Modeling (TLM) for creating virtual platforms and enabling early software/hardware co-verification. Knowledge of Virtual Prototype (VP) development for system-level validation and performance modeling. Pre-silicon Software Co-verification Exposure to software-hardware integration , including early firmware/driver bring-up on virtual or emulated environments. Low-Power Verification Familiarity with power-aware verification methodologies (UPF/CPF) and power intent validation. Leadership in Verification Strategy Experience driving complex multi-IP and SoC-level verification efforts, including coordination with global teams. Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, you can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

Job Title: Senior Design Verification Engineer Experience: 4 – 10 years Location: Siruseri, Chennai (Work from Office only) Industry: Semiconductor / VLSI Role Summary: We are looking for experienced Design Verification Engineers who have built UVM- based testbenches from scratch and contributed to multiple successful tapeouts. Candidates should have deep expertise in functional verification using System Verilog and UVM and be comfortable owning verification deliverables end-to-end. Candidate Requirements:  Education: B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, or related fields.  Experience: 4–10 years of relevant experience in ASIC/SoC design verification.  Must have contributed to at least three or more successful tapeouts. Required Skills:  Strong hands-on experience with SystemVerilog and UVM methodology.  Solid knowledge of SoC/ASIC architecture and verification lifecycle.  Hands-on experience in writing testbenches , stimulus, checkers, monitors, and scoreboards .  Strong debugging skills using simulation tools like VCS, Questa.  Experience with functional and code coverage.  Familiarity with Register Abstraction Layer (RAL) modeling and verification.  Excellent analytical and problem-solving skills.  Strong communication and teamwork abilities.

Job Title: Senior Design Verification Engineer Experience: 4 – 10 years Location: Siruseri, Chennai (Work from Office only) Industry: Semiconductor / VLSI Role Summary We are looking for experienced Design Verification Engineers who have built UVM- based testbenches from scratch and contributed to multiple successful tapeouts. Candidates should have deep expertise in functional verification using SystemVerilog and UVM and be comfortable owning verification deliverables end-to-end. Required Skills  Strong hands-on experience with SystemVerilog and UVM methodology.  Solid knowledge of SoC/ASIC architecture and verification lifecycle.  Hands-on experience in writing testbenches , stimulus, checkers, monitors, and scoreboards .  Strong debugging skills using simulation tools like VCS, Questa.  Experience with functional and code coverage.  Familiarity with Register Abstraction Layer (RAL) modeling and verification.  Excellent analytical and problem-solving skills.  Strong communication and teamwork abilities. Candidate Requirements  Education: B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, or related fields.  Experience: 4–10 years of relevant experience in ASIC/SoC design verification.  Must have contributed to at least three or more successful tapeouts.

Hiring for One of Our Client Job Title: Senior / Lead Design Verification Engineer Experience: 6 – 10 years Location: Siruseri, Chennai (Work from Office only) Industry: Semiconductor / VLSI Employment Type: Full-time / Permanent Key Responsibilities Perform functional verification at block and chip level for complex ASIC/SoC designs. Build UVM-based testbenches from scratch for new IPs or subsystems. Develop and execute detailed verification test plans based on design specifications. Write directed and constrained-random test cases; debug simulation failures. Perform coverage analysis (functional and code) and drive closure. Work with RAL (Register Abstraction Layer) to verify register-level functionality. Develop and validate assertions (SVA) for protocol and functional correctness. Collaborate closely with RTL, DFT, and GLS teams to ensure alignment acrossdesign phases. Participate in multiple tapeouts, ensuring verification quality and delivery. Required Skills Strong hands-on experience with SystemVerilog and UVM methodology. Solid knowledge of SoC/ASIC architecture and verification lifecycle. Hands-on experience in writing testbenches, stimulus, checkers, monitors, and scoreboards . Strong debugging skills using simulation tools like VCS, Questa. Experience with functional and code coverage. Familiarity with Register Abstraction Layer (RAL) modeling and verification. Excellent analytical and problem-solving skills. Strong communication and teamwork abilities. Interested candidates kindly forward your resumr to swetha.s@thompsonshr.com

Job Description We are seeking a Senior Staff Verification Engineer to lead and contribute to the functional verification of complex SoC and IP designs for next-generation AI, HPC, and data center products. The ideal candidate has extensive experience in UVM/SystemVerilog , SoC and IP-level verification, and is passionate about ensuring first-pass silicon success . This role involves defining verification strategies, developing scalable environments, and collaborating cross-functionally with architecture, design, and software teams. Experience with Virtual Modeling, SystemC, and TLM is a plus , enabling advanced verification and early system-level validation. Qualifications Required Qualifications Education & Experience B.S./M.S. in Electrical Engineering, Computer Engineering, or related field. 8+ years of experience in IP/SoC verification with a proven track record of successful silicon delivery. Technical Expertise Deep knowledge of UVM/SystemVerilog for testbench development and verification IP integration. Strong understanding of SoC architecture and protocols such as DDR5, HBM3, PCIe Gen6, CXL 3.0, and other high-speed interfaces. Expertise in coverage-driven verification, constrained-random testing, and assertion-based verification. Proficient in debugging RTL, testbenches, and simulation failures using industry-standard tools. Tools & Languages Hands-on experience with simulation tools (VCS, Xcelium, Questa, etc.), waveform viewers, coverage tools, and automation scripting (Python, Perl, TCL). Preferred/Additional Skills Virtual Modeling and System-Level Verification Familiarity with SystemC and Transaction-Level Modeling (TLM) for virtual prototyping and early system validation. Experience developing or using virtual platforms for hardware/software co-verification is a strong plus. Emulation & Prototyping Exposure to emulation platforms (Palladium, ZeBu) and FPGA-based prototyping for system-level validation and performance analysis. Software Co-verification Experience working alongside firmware/software teams for pre-silicon software validation and early driver/OS bring-up. Low-Power and DFT Verification Knowledge of power-aware verification (UPF/CPF) and DFT validation methodologies is desirable. Additional Information Key Responsibilities Verification Planning & Execution Lead the definition, development, and execution of comprehensive verification plans at IP and SoC levels. Develop UVM/SystemVerilog-based testbenches, including stimulus generation, checkers, and monitors for advanced SoC designs. Drive coverage-driven verification processes, ensuring functional and code coverage goals are met. Cross-Functional Collaboration Collaborate with architecture, RTL design, firmware, software, and emulation teams to define verification requirements and ensure comprehensive test coverage. Participate in design and architecture reviews, providing critical feedback on functionality, testability, and performance considerations. Debug & Issue Resolution Lead debug efforts on complex SoC and IP issues through simulation, emulation, and FPGA prototypes. Perform root-cause analysis and drive issues to closure in partnership with cross-disciplinary teams. Methodology & Infrastructure Development Enhance and maintain verification methodologies, including reusable verification IP, automation scripts, and regression infrastructure. Evaluate and adopt new tools and verification technologies to improve quality and efficiency. Leadership & Mentorship Provide technical guidance and mentorship to junior verification engineers. Lead verification reviews and strategy discussions, ensuring high technical standards and best practices. Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, You Can Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

Job Description Job Summary We are seeking a Principal Verification Engineer to lead the functional verification of complex SoCs and IP blocks for next-generation high-performance computing (HPC), AI acceleration, and data center products. The ideal candidate will have deep experience in SoC/IP functional verification , UVM/SystemVerilog , and coverage-driven methodologies , with a strong focus on ensuring first-pass silicon success. In this leadership role, you will drive end-to-end verification strategy , collaborate cross-functionally with architecture and design teams, and influence product definition through early design engagement. Experience in Virtual Modeling, SystemC, and TLM is a strong plus , enabling advanced verification flows and early software co-development. Key Responsibilities Verification Planning & Execution Own the definition and implementation of IP and SoC-level verification plans, including test strategy, coverage goals, and schedule. Develop UVM/SystemVerilog-based testbenches for complex IP and SoC subsystems, focusing on scalability, reuse, and maintainability. Lead coverage closure activities, including functional, code, and formal coverage, to ensure comprehensive verification. Cross-Functional Collaboration Work closely with RTL designers, architects, firmware/software teams, and post-silicon validation to align on requirements and drive co-verification strategies. Participate in architecture and microarchitecture reviews, providing verification insights and influencing design for testability and verification efficiency. Debug & Root Cause Analysis Perform advanced debug and root cause analysis of complex functional issues, collaborating with cross-disciplinary teams to drive resolutions. Utilize industry-standard tools for waveform analysis, simulation debug, and emulation/prototyping platforms. Methodology & Process Improvement Define and drive best practices in verification methodology, including constrained-random testing, assertion-based verification, and coverage-driven approaches. Contribute to automation and regression flows, optimizing for quality and turnaround time. Technical Leadership & Mentorship Mentor junior verification engineers, guide technical reviews, and contribute to team development and growth. Champion a culture of technical excellence, innovation, and continuous improvement. Qualifications Required Qualifications Education & Experience B.S./M.S. in Electrical Engineering, Computer Engineering, or related discipline. 10+ years of hands-on experience in IP and/or SoC verification with a track record of successful silicon products. Technical Expertise Proven expertise in UVM/SystemVerilog for developing scalable, reusable verification environments. Strong understanding of complex SoC designs, including memory controllers (DDR5, HBM3), PCIe, CXL, and high-speed interfaces. Experience with coverage-driven verification and closure techniques (functional, code, assertion coverage). Solid background in debugging RTL issues, simulation-based testing, and interaction with emulation/FPGA prototyping teams. Verification Tools & Languages Proficient in simulation tools (VCS, Questa, Xcelium), waveform viewers, and scripting languages (Python, Perl, TCL) for automation. Familiarity with formal verification tools and techniques is a plus. Additional Information Preferred/Additional Skills Virtual Modeling and System-Level Verification Experience with SystemC and Transaction-Level Modeling (TLM) for creating virtual platforms and enabling early software/hardware co-verification. Knowledge of Virtual Prototype (VP) development for system-level validation and performance modeling. Pre-silicon Software Co-verification Exposure to software-hardware integration, including early firmware/driver bring-up on virtual or emulated environments. Low-Power Verification Familiarity with power-aware verification methodologies (UPF/CPF) and power intent validation. Leadership in Verification Strategy Experience driving complex multi-IP and SoC-level verification efforts, including coordination with global teams. Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, You Can Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

Qualcomm India Private Limited is seeking a talented individual to join their Hardware Engineering team. As a part of the Engineering Group, you will be responsible for ASIC design with a focus on digital front end design. The ideal candidate should hold a PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field, along with 3-5 years of relevant experience in ASIC design. Key responsibilities include RTL coding in Verilog/VHDL/SV for complex designs with multiple clock domains, expertise in bus protocols like AHB, AXI, and NOC designs, and experience in low power design methodology and clock domain crossing designs. Additionally, the candidate should have experience in Spyglass Lint/CDC checks, waiver creation, formal verification with Cadence LEC, and understanding of the full RTL to GDS flow to collaborate with DFT and PD teams. Desired qualifications for this role also include experience in mobile Multimedia/Camera design, DSP/ISP knowledge, working knowledge of timing closure, expertise in Perl, TCL language, post-Si debug, and good documentation skills. The ability to create a unit level test plan is essential for this position. Minimum qualifications for this role include a Bachelor's degree with 4+ years of Hardware Engineering experience, a Master's degree with 3+ years of relevant experience, or a PhD with 2+ years of related work experience. Qualcomm is an equal opportunity employer and is committed to providing reasonable accommodations for individuals with disabilities during the application/hiring process. If you are looking to be a part of a dynamic team where your skills and expertise will be valued, consider applying for this exciting opportunity at Qualcomm India Private Limited. For further information about this role, please reach out to Qualcomm Careers.,

IP Verification Engineer -SoC Verification Engineer -Design verification Engineer- C Based System Verification engineer) experience: 8+ years location : Cambridge, United Kingdom, immediate joiners preferred Onsite opportunity JD: Responsibilities: Strong verification experience with knowledge of SystemVerilog, UVM System verification (C based) experience is a must. Good knowledge of testplan creation and tracking. Low-level programming experience including C and Assembler. Experience with full verification flow including coverage closure. Experience with ARM-based designs and/or ARM System Architectures AXI, CHI protocol knowledge,

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for SoCs. Experience in Verilog/System-Verilog is a must. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is required. Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience creating pad ring and working with the chip level floorplan team is an added advantage Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 3-6 yrs of experience Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.,

Job Description : We are looking for experienced DV Engineers with a strong background in ARM-based SoC and Subsystem Verification to join our team for exciting semiconductor projects. Key Responsibilities : Perform Design Verification of ARM-based SoC / SS level components Work on Cortex-A / Cortex-M series SoC Debug using CoreSight infrastructure (implementation or validation) Handle RTL / GLS regressions and perform deep simulation-level debugging Develop or maintain testbenches, checkers, and scoreboards in SystemVerilog/UVM Implement C/C++ modeling as needed for verification environments Technical Skills Required : Strong hands-on in SystemVerilog, UVM Experience with ARM protocols : AXI, AHB, APB, CHI, ACE Solid debugging in NoC, memory subsystems Proficiency in C/C++ Exposure to GLS (Zero delay, SDF, PA GLS) simulations is a plus Knowledge of memory protocols: LPDDR4, LPDDR5, DDR, HBM preferred Experience in PCIe, CXL, Ethernet protocols is a plus Scripting (Python, Perl) – good to have for automation and flow enhancements Desired Candidate Profile : 5+ years of experience in DV Must be proactive , with strong debugging & simulation skills Capable of working independently or as part of a dynamic team How to Apply : Email your CV to: Richa.smriti@orcapod.work , contact: +91 92349 19275