526 Systemverilog Jobs - Page 6

As a member of the Cadence team, you will have the opportunity to contribute to the world of technology by designing and implementing DFT IP using Verilog/SystemVerilog and/or VHDL. Your responsibilities will include designing and implementing RTL for DFT IP, including POST and IST. You will play a key role in developing synthesis automation for DFT IP, which involves synthesis and timing constraints, RTL insertion, and verification. Additionally, you will be responsible for owning, maintaining, extending, and enhancing existing DFT IP such as LBIST. Join us in our mission to make a difference in the technology industry. Be a part of our team and help us tackle challenges that others cannot.,

As a Senior Design Verification Engineer, you will be responsible for designing and implementing UVM-based testbenches from scratch and playing a crucial role in the successful tapeouts of multiple projects. Your expertise in functional verification using SystemVerilog and UVM will be essential in owning verification deliverables end-to-end. Your experience should demonstrate a strong command over SystemVerilog and UVM methodology, coupled with a solid understanding of SoC/ASIC architecture and the verification lifecycle. You will be expected to write testbenches, develop stimulus, checkers, monitors, and scoreboards, and utilize simulation tools like VCS and Questa for debugging purposes. In addition, your familiarity with functional and code coverage, as well as Register Abstraction Layer (RAL) modeling and verification, will be vital in ensuring the quality and completeness of the verification process. Your excellent analytical and problem-solving skills will be put to the test as you work collaboratively within a team environment to achieve project goals. To qualify for this role, you must hold a B.E/B.Tech or M.E/M.Tech degree in Electronics, Electrical, or a related field, along with 4 to 10 years of relevant experience in ASIC/SoC design verification. A track record of contributing to at least three or more successful tapeouts will further strengthen your candidacy for this position.,

About Us: At Dabster, we specialize in connecting top talent with leading global companies. We are currently seeking a " Design Verification Engineer " to join one of our key clients on a Fixed term tract with strong potential for extension. Our mission is to be the foremost recruitment specialist in securing exceptional talent for a diverse range of global clients. This is a UK/EU-based role, and visa sponsorship will be provided for eligible candidates. Who Will You Work With: A leading semiconductor and software design company specializing in energy-efficient microprocessor architectures. Its processor designs power the vast majority of smartphones, tablets, embedded systems, and IoT devices worldwide. By licensing its technology to global tech giants, the company plays a pivotal role in the modern computing and electronics ecosystem. About the Role: As a Design Verification Engineer , you should be expertise in SystemVerilog and UVM to develop and execute comprehensive verification plans, build UVM testbenches, and perform block to SoC-level verification. Proficiency in simulation tools, scripting for automation, and advanced debug techniques is essential. Key Responsibilities: Define and execute comprehensive verification plans based on design specifications and architecture. Develop and maintain UVM-based testbenches and environments. Write, simulate, and debug testcases using SystemVerilog. Perform block-level and subsystem-level verification, ensuring alignment with functional and performance targets. Run regression tests, analyse coverage reports, and identify design bugs. Collaborate with RTL designers, integration engineers, and system architects to ensure high-quality deliverables. Support gate-level simulations, formal verification, and other advanced verification methodologies. Preferred Skills: Proven experience with SystemVerilog and UVM methodology. Strong understanding of digital design concepts and verification principles. Experience with tools such as Synopsys VCS, Cadence Xcelium , or Mentor Questa . Familiarity with scripting languages like Python, Perl, or Tcl for automation. Solid grasp of coverage-driven verification and assertion-based verification techniques. Experience with regression management , debug tools like Verdi , and waveform analysis . Exposure to IP/subsystem/SoC-level verification is a plus. What We Offer: Contract Type: 6-months contract with possible extension Remote Flexibility: Fully remote Collaborative Environment: Work closely with industry-leading teams and contribute to cutting-edge projects. This is a UK/EU-based role, and visa sponsorship will be provided for eligible candidates. How to apply: Please submit your CV with relevant experience via LinkedIn Easy Apply or directly to Sushma.gungi@dabster.net. Interview Process: The process typically includes one or two rounds of technical interviews followed by a business alignment discussion.

Job Description: We are looking for skilled Design Verification Engineers with 5-10 years of strong experience in the semiconductor domain. Ideal candidates will have hands-on experience in SystemVerilog (SV) and UVM , along with a solid understanding of SoC/IP level verification , GLS , and CPU verification . Key Skills Required: SystemVerilog (SV) UVM (Universal Verification Methodology) SoC/IP Level Verification GLS (Gate-Level Simulation) CPU/Sub-system Verification High-speed interface protocols: PCIe, DDR, Ethernet Requirements: Immediate to 30 days joiners only Willing to work from office (Bengaluru or Hyderabad) Strong debugging and problem-solving skills Excellent communication and team collaboration abilities

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly skilled and motivated ASIC Digital Design Engineer with a relentless passion for innovation and a commitment to excellence. Your deep expertise in digital design and verification is matched by your curiosity and willingness to tackle complex challenges. You have a solid foundation in microprocessor architectures and are adept at developing and maintaining hardware-software co-simulation environments. Your analytical mindset enables you to create comprehensive functional and code coverage models, and you handle regression testing with precision and care. Your technical toolkit is robust: you are fluent in HDL and verification languages such as SystemVerilog and Verilog, and you bring strong programming skills in C, C++, assembly, Python, and Perl. You are comfortable using RTL simulators and verification tools and are always eager to expand your technical horizons by learning new methodologies. Collaboration is second nature to you—you thrive in multi-cultural, multi-time zone teams and foster inclusive teamwork. Your excellent communication skills ensure that your ideas are heard and understood, and you enjoy sharing your knowledge while learning from others. You take pride in delivering high-quality, reliable work, and you are driven by the opportunity to make a meaningful impact on the future of technology. What You’ll Be Doing: Developing and automating advanced testbenches for ARC processor verification processes. Creating and maintaining functional coverage models and analyzing coverage reports for completeness and effectiveness. Performing comprehensive code coverage analysis to ensure thorough verification and identify potential gaps. Integrating both third-party and internal verification IPs into verification environments. Managing regression testing cycles, analyzing results, and ensuring robust test coverage across all features. Collaborating with multi-site and multi-cultural teams to drive next-generation ARC processor verification projects. Contributing to the improvement of verification methodologies and automation flows. The Impact You Will Have: Ensuring the reliability and high performance of next-generation ARC-V processors. Contributing to the delivery of cutting-edge silicon IP solutions that power industry-leading products. Enhancing the efficiency and effectiveness of verification techniques and processes. Reducing time-to-market for high-performance, low-risk products through rigorous verification. Championing collaboration and knowledge sharing across global engineering teams. Helping Synopsys maintain and strengthen its leadership position in the semiconductor industry. What You’ll Need: Bachelor’s degree in engineering or a related technical field (required). 4+ years of experience in digital design and verification, with a proven track record of success. Strong knowledge of digital design principles and methodologies. Proficiency in SystemVerilog, Verilog, C, C++, assembly, Python, and Perl. Hands-on experience with RTL simulators and verification tools. Experience with microprocessor architectures (RISC-V experience is a significant plus). Who You Are: An excellent communicator with strong verbal and written skills. A collaborative team player who thrives in a multi-cultural, multi-time zone environment. Analytically minded with exceptional problem-solving skills and attention to detail. Adaptable and eager to learn new technologies, tools, and methodologies. Self-driven, proactive, and passionate about delivering high-quality, reliable results. The Team You’ll Be A Part Of: You will be a key member of the Synopsys DesignWare ARC Processor hardware team, working alongside talented engineers on next-generation ARC processor verification. The team is dedicated to developing and maintaining advanced verification environments, ensuring the high performance and reliability of our silicon IP solutions. You will collaborate with colleagues across various locations and time zones, contributing to innovative projects that drive the semiconductor industry forward. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: ASIC / IP Verification THE ROLE: The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s graphics processor IP, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements PREFERRED EXPERIENCE: Proficient in IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++ Graphics pipeline knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment. Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Good working knowledge of SystemC and TLM with some related experience. Scripting language experience: Perl, Ruby, Makefile, shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to video codec system or other multimedia solutions. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-MK1 Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description We are seeking a highly skilled and experienced Staff Engineer for Functional Modeling & Verification to join our innovative team in Bengaluru, India. As a Staff Engineer, you will play a crucial role in shaping our technical direction, leading complex projects, and mentoring junior engineers. Develop Functional Models using C++ and SystemC Collaborate with product managers and other stakeholders to define technical requirements and solutions Conduct code reviews and ensure code quality across projects Identify and resolve complex technical issues across multiple projects Stay current with emerging technologies and industry trends, recommending innovations to improve our tech stack Contribute to the development of engineering best practices and coding standards Participate in system design discussions and technical planning sessions Optimize existing systems for improved performance and scalability Hands-on experience in C++ & System C based Model development/test creation Prior Experience with C based Tests/Test bench development Python coding would be a plus Knowledge on NAND concepts will be an advantage Knowledge on Memory and Digital Design Concepts would be preferable (SRAM/DRAM/ROM/Flash) Circuits/Logic Languages Expertise - C, C++, Python, System C, SystemVerilog/UVM will be a plus - Tool Expertise VisualStudio, Git, Bitbucket Hands-on contributions coding C++ & System C models & test creation Debug issues in Firmware environment Validating the developed model using SV/UVM testbench Debug failures and root-cause it by interacting with other teams/groups Etc. Qualifications 4+ years of RTL Design experience Skills Required/Preferred: Qualifications Bachelor's or Master's degree in Computer Science or a related field BE/BTech/ME/MTech in Engineering with Computer Science, ECE or related field MSc/MCA in Computer Science or a related field Software engineering experience, with a proven track record of leading complex technical projects Experience in one or more programming languages such as Java, Python, or C++ Strong experience with cloud platforms (e.g., AWS, Azure, GCP) and distributed systems In-depth knowledge of system design, architecture, and performance optimization Proficiency in version control systems, preferably Git Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at jobs.accommodations@sandisk.com to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.

Embedded Domain RTL/FPGA Design Engineer(Fresher) Min 0 - 3 Years of Experience BE/B.Tech in Electronics/Electronics & Communication or ME/M.Tech in Electronics/VLSI Design or closely related degree Ahmedabad, Bangalore Roles & Responsibilities RTL programming (Verilog/System Verilog or VHDL). Knowledge of complete FPGA Design Development flow. Hands-on with FPGA Development Tools (Quartus, Modelsim, Vivado, Xilinx ISE, Libero, etc.). Functional verification using Verilog/System Verilog or VHDL. RTL Code Optimization to meet timings and fit on-chip resources. Support all phases of FPGA based product development activities. System Architecture Design. Testing and troubleshooting of hardware. Skills Requirements BE/B.Tech in Electronics/Electronics & Communication from a recognized university with a good academic record. ME/M.Tech in Electronics/VLSI Design from a recognized university with a good academic record. Experience with Verilog/SystemVerilog or VHDL for design and verification. In-depth understanding of FPGA design flow/methodology, IP integration, and design collateral. Should be able to develop the small blocks of IP from scratch and do basic functional verification. Should be familiar with protocols like SPI, I2C, UART and AXI. Understanding of standard/specification/application for IP design or system design. Knowledge of Altera Quartus II Tool, Questasim, Modelsim. Knowledge of Xilinx tools like ISE, and Vivado. Knowledge of Microsemi tools like libero. Knowledge of USB, Ethernet, and external memories such as DDR, QDR RAM and QSPI-NOR based Flash. Personal Competency Self-motivated to learn and contribute. Ability to work effectively with global teams. Able and willing to work in a team-oriented, collaborative environment. A demonstrated ability to prioritize and execute tasks so as to achieve goals in an innovative, fast-paced, and often high-pressure environment. Proven analytical and creative problem-solving abilities. Passionate about writing clean and neat code that adheres to coding guidelines. Apply Now Related Job Openings Embedded Domain Embedded Software Engineer(Experienced) Min 3 - 7 Years of Experience Ahmedabad, Bangalore Read more details Embedded Domain Embedded Software Engineer(Fresher) Min 0 - 3 Years of Experience Ahmedabad, Bangalore Read more details Embedded Domain RTL/FPGA Design Engineer(Experienced) Min 3 - 7 Years of Experience Ahmedabad, Bangalore Read more details

Embedded Domain RTL/FPGA Design Engineer(Experienced) Min 3 - 7 Years of Experience BE/B.Tech in Electronics/Electronics & Communication or ME/M.Tech in Electronics/VLSI Design or closely related degree Ahmedabad, Bangalore Roles & Responsibilities RTL programming (Verilog/System Verilog or VHDL). Knowledge of complete FPGA Design Development flow. Hands-on with FPGA Development Tools (Quartus, Modelsim, Vivado, Xilinx ISE, Libero, etc.). Functional verification using Verilog/System Verilog or VHDL. RTL Code Optimization to meet timings and fit on-chip resources. Support all phases of FPGA based product development activities. System Architecture Design. Testing and troubleshooting of hardware. Skills Requirements BE/B.Tech in Electronics/Electronics & Communication from a recognized university with a good academic record. ME/M.Tech in Electronics/VLSI Design from a recognized university with a good academic record. Experience with Verilog/SystemVerilog or VHDL for design and verification. In-depth understanding of FPGA design flow/methodology, IP integration, and design collateral. Should be able to develop the small blocks of IP from scratch and do basic functional verification. Should be familiar with protocols like SPI, I2C, UART and AXI. Understanding of standard/specification/application for IP design or system design. Knowledge of Altera Quartus II Tool, Questasim, Modelsim. Knowledge of Xilinx tools like ISE, and Vivado. Knowledge of Microsemi tools like libero. Knowledge of USB, Ethernet, and external memories such as DDR, QDR RAM and QSPI-NOR based Flash. Personal Competency Self-motivated to learn and contribute. Ability to work effectively with global teams. Able and willing to work in a team-oriented, collaborative environment. A demonstrated ability to prioritize and execute tasks so as to achieve goals in an innovative, fast-paced, and often high-pressure environment. Proven analytical and creative problem-solving abilities. Passionate about writing clean and neat code that adheres to coding guidelines. Apply Now Related Job Openings Embedded Domain Embedded Software Engineer(Experienced) Min 3 - 7 Years of Experience Ahmedabad, Bangalore Read more details Embedded Domain Embedded Software Engineer(Fresher) Min 0 - 3 Years of Experience Ahmedabad, Bangalore Read more details Embedded Domain RTL/FPGA Design Engineer(Experienced) Min 3 - 7 Years of Experience Ahmedabad, Bangalore Read more details

Minimum qualifications: Bachelor’s degree in Electrical/Computer Engineering or equivalent practical experience. 2 years of experience with RTL design using Verilog/System Verilog and microarchitecture. Experience in ARM-based SoCs, interconnects and ASIC methodology. Preferred qualifications: Master’s degree in Electrical/Computer Engineering. Experience with methodologies for RTL quality checks (e.g., Lint, CDC, RDC). Experience with methodologies for low power estimation, timing closure, synthesis. About The Job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As part of our platform IP team, you will be a part of a team that designs foundation and chassis IPs (NoC, Clock, Debug, IPC, MMU and other peripherals) for Pixel SoCs. You will collaborate with members of architecture, software, verification, power, timing, synthesis, etc. to specify and deliver quality RTL. You will solve technical problems with innovative micro-architecture, low power design methodology and evaluate design options with complexity, performance and power. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Define microarchitecture details such as interface protocol, block diagram, data flow, pipelines, etc. Perform RTL development (SystemVerilog), debug functional/performance simulations. Perform RTL quality checks including Lint, CDC, Synthesis, UPF checks. Participate in synthesis, timing/power estimation, and FPGA/silicon bring-up. Communicate and work with multi-disciplined and multi-site teams. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .

Role Description We are looking for an experienced and passionate Design and Verification Trainer to train and mentor aspiring engineers in RTL design , functional verification , and VLSI concepts . The ideal candidate should have hands-on experience with front-end design and verification methodologies and be comfortable delivering technical content in a structured, engaging, and clear manner. Required Skillsets Strong knowledge of hardware description languages like Verilog/System Verilog Proficiency in verification methodologies such as Universal Verification Methodology (UVM)/ SystemVerilog Assertions (SVA) is crucial Experience with simulation and debugging tools (e.g. Synopsys VCS/VERDI, Spyglass) Proficiency in Scripting Analytical and Problem Solving Skills Qualifications Master's degree in Electronics/VLSI Design (Preferable) Curriculum Development expertise Teaching and Instructional Design abilities Training experience Excellent communication and presentation skills Experience in VLSI design or semiconductor industry Design Thinking skills

Location – Noida, Hyderabad: AMS Layout Engineers – 4 Positions AMS Design / Verification / Layout Engineers – 8 Positions Experience: 4 to 10 Years Job Type: Full-time (On-site) Notice Period: Immediate to 30 Days preferred Role Categories AMS Design Engineer Experience in Analog and Mixed Signal circuit design Strong understanding of CMOS, PLLs, ADCs, DACs, LDOs, Oscillators, and Power Management blocks AMS Verification Engineer Hands-on experience in AMS simulation techniques using Verilog-AMS or SystemVerilog-AMS Good exposure to mixed-signal testbench development and verification methodology AMS Layout Engineer Deep knowledge of analog/mixed-signal layout including matching, shielding, floor planning, and DRC/LVS checks Experience with layout tools such as Virtuoso, Calibre, etc. Desired Skills Solid understanding of analog and mixed-signal concepts Proficiency with industry-standard EDA tools (Cadence Virtuoso, Spectre, Calibre, etc.) Prior experience in tape-outs at advanced technology nodes (28nm and below is a plus) Strong communication and collaboration skills Skills: systemverilog-ams,shielding,ams design,power management blocks,dacs,drc,adcs,floor planning,matching,ams simulation techniques,layout,signal,drc/lvs checks,layout tools,power management,analog and mixed signal circuit design,verilog-ams,spectre,ldos,ams layout,ams verification,virtuoso,design,mixed-signal testbench development,calibre,oscillators,cadence,cmos,plls,cadence virtuoso,lvs,analog/mixed-signal layout

Location – Noida, Hyderabad: AMS Layout Engineers – 4 Positions AMS Design / Verification / Layout Engineers – 8 Positions Experience: 4 to 10 Years Job Type: Full-time (On-site) Notice Period: Immediate to 30 Days preferred Role Categories AMS Design Engineer Experience in Analog and Mixed Signal circuit design Strong understanding of CMOS, PLLs, ADCs, DACs, LDOs, Oscillators, and Power Management blocks AMS Verification Engineer Hands-on experience in AMS simulation techniques using Verilog-AMS or SystemVerilog-AMS Good exposure to mixed-signal testbench development and verification methodology AMS Layout Engineer Deep knowledge of analog/mixed-signal layout including matching, shielding, floor planning, and DRC/LVS checks Experience with layout tools such as Virtuoso, Calibre, etc. Desired Skills Solid understanding of analog and mixed-signal concepts Proficiency with industry-standard EDA tools (Cadence Virtuoso, Spectre, Calibre, etc.) Prior experience in tape-outs at advanced technology nodes (28nm and below is a plus) Strong communication and collaboration skills Skills: systemverilog-ams,shielding,ams design,power management blocks,dacs,drc,adcs,floor planning,matching,ams simulation techniques,layout,signal,drc/lvs checks,layout tools,power management,analog and mixed signal circuit design,verilog-ams,spectre,ldos,ams layout,ams verification,virtuoso,design,mixed-signal testbench development,calibre,oscillators,cadence,cmos,plls,cadence virtuoso,lvs,analog/mixed-signal layout

Category Engineering Hire Type Employee Job ID 12140 Remote Eligible No Date Posted 13/07/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly skilled and motivated ASIC Digital Design Engineer with a relentless passion for innovation and a commitment to excellence. Your deep expertise in digital design and verification is matched by your curiosity and willingness to tackle complex challenges. You have a solid foundation in microprocessor architectures and are adept at developing and maintaining hardware-software co-simulation environments. Your analytical mindset enables you to create comprehensive functional and code coverage models, and you handle regression testing with precision and care. Your technical toolkit is robust: you are fluent in HDL and verification languages such as SystemVerilog and Verilog, and you bring strong programming skills in C, C++, assembly, Python, and Perl. You are comfortable using RTL simulators and verification tools and are always eager to expand your technical horizons by learning new methodologies. Collaboration is second nature to you—you thrive in multi-cultural, multi-time zone teams and foster inclusive teamwork. Your excellent communication skills ensure that your ideas are heard and understood, and you enjoy sharing your knowledge while learning from others. You take pride in delivering high-quality, reliable work, and you are driven by the opportunity to make a meaningful impact on the future of technology. What You’ll Be Doing: Developing and automating advanced testbenches for ARC processor verification processes. Creating and maintaining functional coverage models and analyzing coverage reports for completeness and effectiveness. Performing comprehensive code coverage analysis to ensure thorough verification and identify potential gaps. Integrating both third-party and internal verification IPs into verification environments. Managing regression testing cycles, analyzing results, and ensuring robust test coverage across all features. Collaborating with multi-site and multi-cultural teams to drive next-generation ARC processor verification projects. Contributing to the improvement of verification methodologies and automation flows. The Impact You Will Have: Ensuring the reliability and high performance of next-generation ARC-V processors. Contributing to the delivery of cutting-edge silicon IP solutions that power industry-leading products. Enhancing the efficiency and effectiveness of verification techniques and processes. Reducing time-to-market for high-performance, low-risk products through rigorous verification. Championing collaboration and knowledge sharing across global engineering teams. Helping Synopsys maintain and strengthen its leadership position in the semiconductor industry. What You’ll Need: Bachelor’s degree in engineering or a related technical field (required). 4+ years of experience in digital design and verification, with a proven track record of success. Strong knowledge of digital design principles and methodologies. Proficiency in SystemVerilog, Verilog, C, C++, assembly, Python, and Perl. Hands-on experience with RTL simulators and verification tools. Experience with microprocessor architectures (RISC-V experience is a significant plus). Who You Are: An excellent communicator with strong verbal and written skills. A collaborative team player who thrives in a multi-cultural, multi-time zone environment. Analytically minded with exceptional problem-solving skills and attention to detail. Adaptable and eager to learn new technologies, tools, and methodologies. Self-driven, proactive, and passionate about delivering high-quality, reliable results. The Team You’ll Be A Part Of: You will be a key member of the Synopsys DesignWare ARC Processor hardware team, working alongside talented engineers on next-generation ARC processor verification. The team is dedicated to developing and maintaining advanced verification environments, ensuring the high performance and reliability of our silicon IP solutions. You will collaborate with colleagues across various locations and time zones, contributing to innovative projects that drive the semiconductor industry forward. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Key Responsibilities: Develop AMS verification environments from the ground up using SystemVerilog/UVM Own and execute test planning, AMS setup, and mixed-signal simulation Work on SerDes verification involving high-speed protocols (PCIe, USB 3.0, MIPI, etc.) Model and verify analog/mixed-signal blocks using wreal , RNM , and Verilog-A Perform simulations using VCS Primesim AMS and Primesim XA tools Collaborate closely with analog, digital, and system teams for integrated AMS verification

Key Responsibilities: Hands-on microarchitecture and RTL development for IP blocks Develop microarchitecture based on design specifications, including HW-SW interface definition IP-level verification and debugging for video and audio subsystems Work on MIPI CSI and DSI protocols understanding at protocol and implementation level Collaborate with design, verification, and software teams to ensure high-quality deliverables Drive or contribute to test plan creation, environment development, and coverage closure

Job Description: We are looking for an experienced SoC DV Lead with a strong background in SoC verification and hands-on experience in writing C test cases for SoC-level DV. Key Responsibilities: Lead SoC DV activities from planning to closure Develop and debug C-based test cases for system-level verification Work closely with design, architecture, and firmware teams Perform coverage analysis and ensure comprehensive validation Guide and mentor junior DV engineers Key Skills: SoC-level design verification C programming for test development Debugging and problem-solving Exposure to UVM/SystemVerilog (preferred) Strong understanding of SoC architecture

Location Karnataka Bengaluru Experience Range 8 - 10 Years Job Description Senior IO-MMU Design Engineer Role Overview: Leads the design and integration of IO Memory Management Units (IO-MMUs) for secure, virtualized, and high-performance SoC architectures. Key Responsibilities: Architect and implement RTL for IO-MMU subsystems Define IO translation and access control logic Collaborate with SoC, interconnect, and virtual memory teams Ensure compliance with IOMMU standards (SMMU, PCIe ATS/PRI, RMRR) Deliver Lint, CDC, synthesis, and DFT clean designs Required Skills: 8+ years of experience in SoC and IP-level RTL design Strong in SystemVerilog, with knowledge of memory protection and address translation Experience with SoC virtual memory systems and PCIe/AXI protocols Familiar with coherency, TLB, page walk and IOVA mechanisms Skilled in timing closure and formal/CDC tools

Location Karnataka Bengaluru Experience Range 8 - 10 Years Job Description Senior IO-MMU Verification Engineer Role Overview: Responsible for functional verification of IO-MMU units, focusing on translation, protection, and system interaction with DMA/IP blocks. Key Responsibilities: Develop UVM-based environments for IO-MMU verification Create tests for virtual address translation, permissions, and fault injection Verify compliance with protocols like PCIe ATS, PRI, and ARM SMMU Collaborate with SoC-level teams for system integration and validation Drive functional and code coverage closure Required Skills: 8+ years in verification of memory or IO subsystems Expertise in UVM, SystemVerilog, SVA Strong debugging and protocol knowledge (AXI, PCIe, SMMU) Experience with constrained-random and assertion-based verification Familiar with trace analysis and formal verification integration

As an AMS Verification Engineer, you will play a crucial role in ensuring the successful verification of Analog Mixed Signal designs. With a minimum of 5 years of experience in this field, you will be responsible for developing and executing verification plans, creating testbenches, and collaborating with design teams to guarantee that designs meet specifications. Your key skills will include strong RNM modeling proficiency, hands-on experience with Cadence AMS/DMS flow, familiarity with SystemVerilog and Verilog-AMS, and a solid understanding of analog and mixed-signal design principles. Additionally, you should have expertise in UVM, the ability to debug AMS modeling issues, and experience with basic scripting and automation. Your responsibilities will involve building and maintaining SystemVerilog real number models, verifying AMS/DMS IP/chip functionality, and ensuring effective communication and documentation throughout the verification process. By working closely with both analog and digital design teams, you will contribute to the successful verification of complex AMS designs. If you are a detail-oriented verification engineer with a passion for analog mixed-signal design and a strong background in AMS verification, this role offers an exciting opportunity to further your career in a dynamic and collaborative environment.,

Experience: 5 Years Location: Bangalore/Hyderabad Education: B.E/B.Tech in ECE/EEE or M.E/M.Tech in VLSI/Electronics Roles and Responsibilities DDR Verification: Lead the verification of DDR memory controller and PHY designs, ensuring compliance with DDR standards such as DDR3, DDR4, DDR5, and other memory interface protocols. Testbench Development: Develop and implement scalable, reusable, and efficient verification environments and testbenches for DDR designs using SystemVerilog, UVM (Universal Verification Methodology), and other industry-standard verification methodologies. Protocol Compliance: Ensure the DDR design meets protocol specifications, including command, data, and clock synchronization, read/write cycles, burst transfers, refresh cycles, error handling, and power management. Verification Plan Creation: Develop detailed verification plans based on DDR specifications and requirements, ensuring full coverage of corner cases, timing, and protocol validation. Simulation & Debugging: Run simulations and debug issues using tools such as Questa, VCS, or ModelSim, applying advanced debugging techniques such as waveform analysis, assertion-based verification, and code coverage. Regression Testing: Set up and manage regression testing for DDR functionality to ensure continuous validation and early detection of design issues. Verification Coverage: Achieve high functional and protocol coverage, ensuring that critical aspects of DDR design, including timing constraints, corner cases, and failure scenarios, are thoroughly verified. Formal Verification: Implement formal verification techniques to validate key components of the DDR design, ensuring correctness in timing and data flow, and verifying the most critical operations.

Job Description: We are seeking a skilled professional with expertise in design and validation to join our dynamic and innovative team. The ideal candidate will have a strong background in developing and validating FPGA-based solutions, along with solid knowledge of PCIe, CXL, USB and other protocols. We are looking for someone who is enthusiastic about tackling daily technical challenges, self-motivated, proactive, responsive, persistent, and outstanding in problem-solving. Key Responsibilities: Develop and implement comprehensive validation plans for PCIe, CXL, USB and other interface solutions, ensuring compliance with industry standards and specifications. Design FPGA-based solutions to support Hardware Assisted Verification (HAV). Perform thorough testing and validation of solutions, proactively identifying and resolving issues. Collaborate with design teams to understand architecture and requirements, providing constructive feedback to improve product quality. Document validation processes, results, and key insights, delivering clear and concise reports to stakeholders. Work closely with cross-functional teams to ensure seamless project execution. Stay current with industry trends and advancements in validation methodologies and tools. Qualifications: Bachelor’s or Master’s degree in Electronics, Electrical, or Computer Engineering (or a related field), with at least 8 years of design and validation experience. Extensive knowledge of FPGA-based design and validation methodologies. Strong understanding of high-speed protocols such as PCIe, CXL, and USB. Proficiency in programming languages including C/C++, SystemVerilog, Verilog, Perl, Python, and TCL. Experience with emulation or prototyping platforms (e.g., ZeBu, HAPS) is a plus. Excellent problem-solving skills and keen attention to detail. Strong communication and collaboration abilities, with a proven track record of effective teamwork.

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Join Qualcomm's design verification team in verifying the Digital Low Power IPs for exciting products targeted for 5G, AI/ML, compute, IOT, and automotive applications. The team is responsible for the complete design verification lifecycle (including Functional, Low Power Verification, Gate Simulation, Formal Verification) from system-level concept to tape out and post-silicon support. Responsibilities: Define pre-silicon and post-silicon testplans based on design specs and using applicable standards working closely with design team. Architect and develop the testbench using advanced verification methodology such as SystemVerilog/UVM, Low power verification, Formal verification and Gate level simulation to ensure high design quality. Author assertions in SVA, develop testcases, coverage models, debug and ensure coverage closure. Work with digital design, analog circuit design, modeling, controller/subsystem, & SoC integration teams to complete the successful IP level verification, integration into subsystem and SoC, and post-silicon validation. Minimum Qualifications: Master's/Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field. 8+ years ASIC design verification, or related work experience. Knowledge of a HVL methodology like SystemVerilog/UVM. Experience working with various ASIC simulation/formal tools such as VCS, Xcellium/NCsim, Modelsim/Questa, VCFormal, Jaspergold, 0In and others. Preferred Qualifications: Experience with Low power design verification, Formal verification and Gate level simulation. Knowledge of standard protocols such as Power Management Flows, PCIe, USB, MIPI, LPDDR, etc. will be a value add Experience in scripting languages (Python, or Perl). Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3075495

About This Opportunity We are starting a new Silicon R&D center in Bangalore. Join our team as we pioneer the IPs that power the digital ASICs of tomorrow's mobile standards. Ericsson System on a Chip (SoC) devices are custom-made for mobile networks and spans across the Ericsson Radio System - RAN Compute, Radio and Transport – to enable communication service providers to surpass the expectations of their end-customers. At our state-of-the-art design centers, we don't just follow industry trends—we set them. By leveraging cutting-edge tools and methodologies, we lead innovation in the telecommunications sector. As a valued team member, you'll play a pivotal role in shaping the future of global connectivity, contributing to the advancement of 5G and 6G technologies. As part of our global R&D organization, you'll collaborate with talented teams across Sweden, the US, and beyond. We are committed to fostering a collaborative and innovative work environment that encourages creativity and teamwork. What You Will Do Take charge of delivering high-impact ASIC IP solutions, ensuring alignment with broader project goals and requirements. Creative Freedom: Immerse yourself in an environment that champions innovation and critical thinking. You'll have the opportunity to explore advanced verification technologies alongside skilled experts. Global Impact: Contribute to projects with far-reaching impacts, transforming industries, advancing digital economies, and enhancing communication worldwide. Work-Life Balance: We prioritize the well-being of our team members, offering a balanced work-life environment to help you excel professionally without compromising your personal life. Professional Growth: Engage in continuous learning opportunities, tackle exciting challenges, and collaborate with brilliant minds in a supportive and forward-thinking atmosphere. An international work environment with opportunities for professional growth and development. A collaborative and inclusive culture that values diversity and innovation. A competitive compensation and benefits package. You will bring Key Responsibilities: Lead a team of verification engineers, providing mentorship and guidance to ensure efficient and reusable verification practices. Collect and address, team status and metrics. Take full responsibility for the verification strategies that the team has responsibility for. Define and implement UVM-based test environments. Break down requirements to create a Verification Strategy and develop and execute a Verification Plan. Develop, run, and debug test cases to ensure design quality. Continuously improve and optimize verification methodologies. Generate comprehensive documentation throughout the verification lifecycle. Collaborate closely with other verifiers, designers, and architects. Develop competence in the technical domain. Foster cross-team collaboration to ensure seamless project delivery and integration. Required Qualifications: Bachelor’s degree in electrical or computer engineering. 8+ years of industry experience in verification using SystemVerilog and UVM. Proven track record of leading verification test plan development in cross-site environments. Proficiency in/with: architecting and creating new grounds-up random and directed test environments and testcase strategies. formal verification for connectivity checks and using assertion-based VIPs. architecting and leading implementation of scoreboards, checkers, bus functional models SystemVerilog Assertions. Strong experience in low-power design verification. Additional Requirements: Experience with Cadence or Synopsys verification suites. Team-oriented, prioritizing team success within the team, across teams, and across sites over individual results. Specifically, experienced at communicating and meeting expectations within and across teams in an agile environment. High attention to detail and commitment to quality. Strong focus on meeting project deadlines and deliverables. Proficient in English, with strong communication skills. Preferred Skills: Understanding of radio access systems and their components. Working knowledge of systems for continuous integration (e.g., Jenkins), simulation and analysis environments (e.g., Simscope), issue-tracking (e.g., Jira). Experience in verification in one or more of the following hardware domains: AMBA-based designs especially AXI and CHI. ARM-based real-time microcontroller systems including their control and interface peripherals. Wireless infrastructure specific protocols and interfaces and protocols. Implementation of hardware-based digital signal processing systems (filters, adaptation, etc.) Why join Ericsson? At Ericsson, you´ll have an outstanding opportunity. The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world’s toughest problems. You´ll be challenged, but you won’t be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next. What happens once you apply? Click Here to find all you need to know about what our typical hiring process looks like. Encouraging a diverse and inclusive organization is core to our values at Ericsson, that's why we champion it in everything we do. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity Employer. learn more. Primary country and city: India (IN) || Bangalore Req ID: 766878

Talented and motivated Mid-Level CPU Subsystem Design and Verification Engineer to join our growing team. Responsibilities : Design : Participate in the design of CPU subsystems, collaborating with architects and design engineers. Contribute to micro-architectural decisions, considering performance, power, and area trade-offs. Develop detailed design documents and schematics for assigned subsystems. Verification : Develop comprehensive test plans and verification strategies for assigned subsystems. Create and implement SystemVerilog/UVM testbenches, checkers, and coverage groups. Execute verification plans, analyse results, and debug failures effectively. Work closely with verification engineers and architects to identify and resolve issues. Additional Responsibilities: Stay up-to-date on the latest advancements in CPU architecture and verification methodologies. Contribute to technical discussions and actively participate in design reviews. Collaborate effectively with cross-functional teams to achieve project goals. Qualifications : Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field. 3-5 years of experience in CPU design or verification. Strong understanding of digital design principles, RTL, and verification methodologies (UVM, SystemVerilog). Experience with Verilog/SystemVerilog coding and debugging. Familiarity with CPU microarchitecture concepts and verification best practices. Excellent analytical and problem-solving skills. Strong communication and collaboration skills. Ability to work independently and as part of a team. Benefits : Competitive salary and benefits package. Opportunity to work on cutting-edge technology and make a real impact. Regards, K Himabindu Mail Id: himabindu.jeevarathnam@acldigital.com