RTL/DV

You should have a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field along with 4-10 years of experience in RTL design and Design Verification implementation for VLSI systems. Your expertise should include Verilog, SystemVerilog, and RTL design methodologies, as well as a solid understanding of digital design concepts like pipelining, clock domain crossing, and low-power design techniques. In your role as an RTL Design Engineer, you will be responsible for developing RTL designs for digital IPs, subsystems, and SoCs based on architectural specifications. You will collaborate with architects and system engineers to translate high-level requirements into detailed micro-architecture, perform design optimizations, conduct design reviews, work closely with verification teams, debug and resolve design issues, participate in timing analysis, and document design specifications. As a Design Verification Engineer, you will develop and maintain processor-level verification environments, design and implement test plans, integrate and verify processor subsystems in SoC environments, execute regression tests, analyze simulation results, collaborate with cross-functional teams, and optimize verification flows. You should have expertise in UVM SystemVerilog, processor architectures, AMBA protocols, and C programming for test development. Preferred qualifications include experience with low-power design, advanced process nodes, formal verification methodologies, hardware-software co-design, FPGA prototyping, and familiarity with machine learning or AI-based RTL optimizations. This role is for a Full Time, Permanent position in the Electronic Components / Semiconductors industry under the Hardware category. The educational requirements include a B.Tech/B.E. in Any Specialization for UG and an M.Tech in Any Specialization for PG.,