16 Lowpower Design Jobs

Role Overview: As a Firmware Developer at our company, you will be an integral part of our innovative team, contributing to the development of IoT solutions, robust firmware for embedded devices, and our cloud platforms and mobile applications. Your expertise in C/C++ programming, working with microcontrollers, and real-time embedded system design will be crucial in ensuring the performance, reliability, and scalability of our products. Key Responsibilities: - Design, develop, and optimize firmware for embedded systems using C/C++. - Develop solutions for microcontrollers such as STM32, NXP, PIC, and Texas Instruments. - Work with communication protocols including Bluetooth, USB, UART, Modbus, CAN, I2C, SPI, Ethernet, Wi-Fi, and RF. - Debug hardware using tools such as Digital Storage Oscilloscope (DSO), multimeters, and function generators. - Develop and integrate firmware for RTOS, handle sensor interfacing and signal conditioning. - Collaborate with cross-functional teams to integrate firmware with IoT Cloud Platforms, Desktop Apps, and Mobile Apps. - Ensure firmware aligns with low-power design and optimization requirements. - Provide high-quality documentation and implement unit/system testing. Qualifications: - Degree in Engineering (Computer Science, Data Science, Electronics, or Electrical). Technical Skills: - Proficiency in Embedded C/C++ programming. - Strong hands-on experience with microcontrollers (STM32 preferred, NXP, PIC, Texas Instruments). - Experience with IDEs and tools: IAR Workbench, STM32 Cube IDE, Keil Microvision, CCS, e2 Studio. - Expertise in communication protocols: Bluetooth, USB, UART, Modbus, CAN, I2C, SPI, Ethernet, Wi-Fi, RF. - Strong understanding of RTOS development & integration. - Hardware debugging with oscilloscopes, multimeters, function generators, schematic interpretation. - Familiarity with GPS, GPRS modules, and sensors for embedded applications. - Knowledge of GIT version control and project management tools like Jira. - Understanding of low-power design and optimization. - Familiarity with JSON and API testing tools (e.g., Postman). Soft Skills: - Strong communication and coordination skills. - Analytical thinking and problem-solving abilities. - Effective troubleshooting to identify and resolve issues quickly. - Ability to work independently and within cross-functional teams.,

The ASIC Design Senior Engineer plays a critical role in the development and implementation of advanced integrated circuit designs within the organization. You will be instrumental in driving innovation and ensuring that the products maintain a competitive edge in the rapidly evolving semiconductor industry. Your responsibilities will include contributing technical expertise and leadership in the ASIC design process, from initial concept through to production. Working collaboratively with cross-functional teams, you will solve complex design challenges, optimize performance, and ensure adherence to industry standards. In addition to deep technical knowledge, this role will require the ability to mentor junior engineers and lead project initiatives. Your strong background in digital and analog design, along with a proven track record of delivering projects on time and within budget, will be essential in shaping the future of the technology solutions and impacting the company's success. Key Responsibilities: - Design and validate complex ASICs in accordance with specifications. - Develop RTL using Verilog/System Verilog for various digital components. - Conduct simulation and verification of designs using advanced methodologies. - Execute timing analysis and optimization to meet performance requirements. - Collaborate with cross-functional teams including hardware, software, and test engineering. - Perform power estimation and drive strategies for low-power design. - Oversee the transition from design to tape-out and ensure compliance with DFT standards. - Mentorship and training of junior engineers and interns in design practices. - Participate in design reviews and provide constructive feedback. - Address and resolve design-related issues throughout the lifecycle. - Communicate effectively with project managers to ensure timelines are met. - Document design processes and maintain accurate design records. - Utilize FPGA devices for prototyping and testing of ASIC functionalities. - Research and implement new design tools and methodologies. - Keep updated with industry trends and advancements in ASIC technology. Required Qualifications: - Bachelor's or Master's degree in Electrical Engineering or related field. - Minimum of 5 years of experience in ASIC design and development. - Strong experience with digital circuit design and verification methodologies. - Proficient in Verilog and System Verilog programming. - Hands-on experience with tools such as Cadence, Synopsys, and Mentor Graphics. - Familiarity with FPGA development and prototyping techniques. - Demonstrated experience in timing closure and power optimization. - Solid understanding of DFT concepts and techniques. - Ability to mentor junior engineers and lead design projects. - Excellent problem-solving and analytical skills. - Strong communication skills, both verbal and written. - Ability to work collaboratively in a fast-paced environment. - Knowledge of industry standards and best practices in ASIC design. - Experience with scripting languages such as Perl or Python is a plus. - Strong organizational skills and attention to detail. - Demonstrated track record of successful project delivery. Skills: system verilog, problem solving, simulation and verification, power optimization, DFT, timing analysis, schematic capture, FPGA development, low-power design, DFT standards, SoC, scripting languages (Perl, Python), Verilog, digital circuit design, RTL coding, ASIC design, power estimation.,

You are invited to join our cutting-edge semiconductor team in Hyderabad as an ASIC Design Engineer. With over 8 years of experience in chip design and development, you will play a key role in our innovative projects. Your expertise in RTL Design, Verilog/VHDL, Synthesis, Timing Analysis, and Low-Power Design will be crucial in driving our semiconductor industry forward. If you are passionate about VLSI and eager to tackle exciting challenges, we want to hear from you! Join us and be part of a dynamic team that values innovation and excellence. Take the next step in your engineering career by applying directly or reaching out to us today. Let's work together to create groundbreaking solutions in the world of ASIC Design. #ASICDesign #Semiconductor #VLSI #Hiring #EngineeringJobs #HyderabadJobs,

As a highly skilled Hardware & Firmware Expert with experience in embedded systems and IoT applications, you will be responsible for developing hardware design and firmware for MCUs such as STM32, ESP32, and Nordic nRF series. Your expertise in IoT communication protocols like WiFi, BLE, LoRa, and other LPWAN technologies will be crucial in implementing and integrating these protocols. Additionally, you will work with RTOS-based firmware, optimize tasks for real-time execution, and develop and debug peripheral interfaces including UART, I2C, SPI, ADC, PWM, GPIOs, and DMA. You will also play a key role in implementing and managing OTA firmware upgrades, secure boot mechanisms, writing efficient device drivers, integrating third-party libraries and SDKs, and working with low-power design techniques for battery-operated devices. Your experience in developing firmware using frameworks like Arduino, STM32 HAL/LL, ESP-IDF, and Nordic SDK, and debugging firmware using tools like JTAG, SWD, Logic Analyzers, and Oscilloscopes will be essential for this role. Collaboration with hardware, software, and cloud teams for seamless IoT integration will also be part of your responsibilities. To be successful in this role, you should have 4+ years of experience in firmware development for embedded systems, strong hands-on experience with STM32, ESP32, and Nordic MCUs, proficiency in C/C++ programming for embedded systems, and familiarity with RTOS such as FreeRTOS and Zephyr. Experience with wireless communication protocols, Arduino framework, ESP-IDF, Nordic SDKs, peripheral interfaces, OTA firmware updates, debugging tools, low-power design techniques, and security protocols for embedded IoT devices will be highly valued. Preferred qualifications include experience with AI/ML on edge devices (TinyML), custom bootloaders, secure firmware updates, and knowledge of scripting languages like Python for debugging and automation. In return, you can expect a competitive salary based on experience, a flexible work environment, and the opportunity to work on cutting-edge IoT and embedded projects with learning and growth opportunities in firmware development & IoT solutions. If you are passionate about embedded systems and IoT firmware development, we look forward to hearing from you!,

As a Senior ASIC Physical Design Engineer at Synopsys, you will play a crucial role in shaping the future of the semiconductor industry by driving innovations in IC design and physical implementation. Your expertise in high-performance digital design, low-power design, and high-speed clock design will be instrumental in developing cutting-edge solutions for creating high-performance silicon chips. You will collaborate with cross-functional teams to streamline the physical design process, enhance product offerings, and exceed customer expectations. Your responsibilities will include floor planning, developing timing constraints, physical synthesis, clock tree optimization, routing and extraction management, timing closure, signal integrity analysis, physical verification, and design for manufacturability (DFM) checks. By contributing to the development and enhancement of physical design flows for advanced technology nodes, you will drive innovation and improve efficiency in the physical design process. To excel in this role, you should have a solid understanding of IC design principles and physical implementation, experience with the full design cycle from RTL to GDSII, proficiency in deep sub-micron design flows, and hands-on experience with complex design projects and successful tape-outs. You should be a detail-oriented professional with strong analytical and problem-solving skills, an effective communicator, a proactive learner, a dedicated team player, and a creative thinker who can contribute to innovative solutions and improvements. You will be part of a dynamic and innovative team at Synopsys, dedicated to pushing the boundaries of IC design and physical implementation. Together, you will work collaboratively to address complex challenges and deliver exceptional results, driving the technological advancements that shape the future of the semiconductor industry. Synopsys offers a comprehensive range of health, wellness, and financial benefits to cater to your needs. Your recruiter will provide more details about the salary range and benefits during the hiring process. Join us at Synopsys to transform the future through continuous technological innovation and contribute to the growth of our innovative group.,

You are a highly skilled Senior ATE Test Engineer with expertise in RMA (Return Material Authorization), ATE test programming, debugging, and handling Advantest ATE testers. Your role is crucial in ensuring the reliability, efficiency, and quality of semiconductor testing processes. You will be responsible for developing, debugging, and optimizing ATE test programs for Advantest testers. Additionally, you will support RMA analysis, identify root causes of failures, and implement corrective actions. It will be your duty to maintain and enhance test methodologies to improve efficiency and yield, manage and operate ATE testers, and collaborate with cross-functional teams to enhance testing strategies. Furthermore, you will conduct test hardware debugging, load board characterization, and bring-up activities, analyze test data, troubleshoot failures, and drive continuous improvements. Ensuring compliance with industry standards and customer requirements, documenting test procedures, results, and debugging methodologies for knowledge sharing, as well as training junior engineers and providing technical mentorship are also part of your responsibilities. There are immediate short-term (3-6 months) and long-term (1-2 years) opportunities to visit Japan for onsite work. You must have a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field, along with at least 5 years of experience in ATE testing and post-silicon validation, including 2 years in a leadership or supervisory role. Your technical skills should include expertise in developing ATE test programs for platforms such as Teradyne, Advantest, or similar, proficiency in scripting languages (e.g., Python, Perl) for test automation, a strong understanding of digital and analog circuit design and debugging, familiarity with industry-standard validation tools and methodologies, and familiarity with statistical data analysis tools for yield improvement. You should also have proven leadership skills, strong project management abilities, excellent problem-solving and analytical skills, strong verbal and written communication skills, and the ability to work both independently and in a team environment with attention to detail and a commitment to quality. Preferred qualifications include experience with high-speed interfaces (e.g., PCIe, USB, Ethernet, SGMII, etc), knowledge of FPGA and/or ASIC design and validation, familiarity with low-power design and validation techniques, understanding of system-level validation and testing, knowledge of industry-standard protocols and interfaces (e.g., PCIe, DDR, Ethernet), and experience with design-for-test (DFT) methodologies and scan insertion.,

You should have a Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field with 15 years or more of relevant experience. It is essential to possess experience in use-case analysis and decomposition, as well as proficiency in Linux, Zephyr, Free RTOS, or similar operating systems. A strong understanding of microprocessor and microcontroller architectures, including CPU cores, DSP, memory management, and peripheral integration is required. Additionally, experience in system-level performance optimization, low-power design, SW/HW co-design, and real-time processing is necessary. Familiarity with high-speed interconnects, memory architectures, DDR, PCIe, and bus protocols is also important. Strong collaboration skills are crucial for working across multidisciplinary teams, including silicon, software, hardware, board design, and validation engineers. It is expected that you have experience in product development processes. Preferred qualifications include experience with ARM Cortex and/or RISC-V architecture, media processing, vision and imaging applications, and system-level simulation tools. Familiarity with hardware/software co-design, debugging techniques, Machine Learning Hardware IPs, tools, and architecture is advantageous. Knowledge of functional safety and security standards, as well as Wi-Fi integration, networking protocols, and secure wireless communication, would be beneficial.,

You should have a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field along with 4-10 years of experience in RTL design and Design Verification implementation for VLSI systems. Your expertise should include Verilog, SystemVerilog, and RTL design methodologies, as well as a solid understanding of digital design concepts like pipelining, clock domain crossing, and low-power design techniques. In your role as an RTL Design Engineer, you will be responsible for developing RTL designs for digital IPs, subsystems, and SoCs based on architectural specifications. You will collaborate with architects and system engineers to translate high-level requirements into detailed micro-architecture, perform design optimizations, conduct design reviews, work closely with verification teams, debug and resolve design issues, participate in timing analysis, and document design specifications. As a Design Verification Engineer, you will develop and maintain processor-level verification environments, design and implement test plans, integrate and verify processor subsystems in SoC environments, execute regression tests, analyze simulation results, collaborate with cross-functional teams, and optimize verification flows. You should have expertise in UVM SystemVerilog, processor architectures, AMBA protocols, and C programming for test development. Preferred qualifications include experience with low-power design, advanced process nodes, formal verification methodologies, hardware-software co-design, FPGA prototyping, and familiarity with machine learning or AI-based RTL optimizations. This role is for a Full Time, Permanent position in the Electronic Components / Semiconductors industry under the Hardware category. The educational requirements include a B.Tech/B.E. in Any Specialization for UG and an M.Tech in Any Specialization for PG.,

As an experienced Digital Design Engineer with 3+ years of experience, you will collaborate with system architects to interpret high-level specifications and requirements for digital design. Your responsibilities will include creating RTL descriptions of digital circuits using hardware description languages such as Verilog and SystemVerilog to capture the desired functionality. You will implement digital logic functions, state machines, and control units to meet design goals for performance, power, and area (PPA). In this role, you will work with synthesis tools like Synopsys Design Compiler and Cadence Genus to optimize the RTL code for efficient gate-level implementation. You will address clock domain crossing (CDC) issues by synchronizing signals that cross different clock domains and implement low-power design techniques to reduce power consumption while maintaining functionality. Your tasks will also involve using static timing analysis (STA) tools to ensure that the design meets timing constraints and operates at the desired clock frequency. You will conduct functional simulation and RTL-level verification using tools like ModelSim to verify the correctness of the RTL code. Additionally, you will identify and address issues in the RTL code, collaborating with cross-functional teams to resolve them. Maintaining comprehensive documentation of the RTL code, design constraints, and any design-specific considerations will be essential in this role. You will also be responsible for integrating digital IP blocks from internal or external sources into the overall design, ensuring compatibility and functionality. Collaboration with physical design, verification, and DFT (Design for Test) engineers is crucial to ensure the successful integration of digital components into the complete IC design.,

As an R&D Engineer at Synopsys, you play a crucial role in driving innovation in the field of physical design, with a focus on high-performance cores and IPs. Your deep understanding of physical design, coupled with your expertise in place & route, timing closure, and power optimization, enables you to tackle complex design challenges with ease. Your proficiency in low-power, high-performance design, particularly with advanced nodes under 5nm, sets you apart in the industry. Your responsibilities include developing and implementing innovative methodologies for high-performance cores and IPs, collaborating with a global team to enhance Performance, Power, and Area (PPA) metrics, and utilizing advanced technologies and tools to improve design quality and process efficiency. You will contribute to both flow development and the implementation of complex IPs, addressing critical design challenges using Synopsys implementation tools. Your impact as an R&D Engineer at Synopsys is significant, as you drive innovation in high-performance core and IP implementation methodologies, enhance the efficiency and predictability of the implementation process, and contribute to the development of cutting-edge semiconductor technologies. By solving complex design challenges and supporting the continuous advancement of Synopsys" technological capabilities, you play a key role in achieving best-in-class PPA and TAT targets. To excel in this role, you must possess deep knowledge of physical design, place & route, timing closure, and power optimization, along with experience in low-power, high-performance design and advanced nodes under 5nm. Proficiency in industry-leading tools like Fusion Compiler, Primetime, and Formality, as well as scripting languages such as TCL, Perl, and Python, is essential. A BS or MS in Electrical Engineering or a related field with 5+ years of relevant experience is required. Additionally, your self-motivation, strong investigative and problem-solving skills, enthusiasm for learning new technologies, and excellent communication skills in English are crucial attributes for success in this role. Joining the global team at Synopsys, you will contribute to the advancement of state-of-the-art high-performance cores and IPs implementation. Working with industry-leading tools and technologies, you will be part of a team focused on developing innovative methodologies to implement CPUs/GPUs and interface IPs efficiently. Your role will involve tackling complex design challenges, improving PPA metrics, and achieving best-in-class targets, thereby contributing to the continuous enhancement of Synopsys" technological capabilities.,

We are seeking enthusiastic individuals to join our team at Alphawave Semi, where we enable the next generation of digital technology by accelerating critical data communication. As a Physical Design Engineer in our IP Scaling (IPS) organization, you will play a key role in creating customized IP for our expanding customer base, delivering high-speed interconnect solutions for various industries such as High Performance Computing and Artificial Intelligence. Your responsibilities will include driving the backend process through the entire implementation flow, with a focus on floor-planning, power planning, low-power design, place & route optimization, clock tree synthesis, static timing verification, and physical verification. We are looking for someone with at least 5 years of Physical Design experience, a Bachelor's degree in Electrical or Computer Engineering (or equivalent), and advanced technology node experience. Attention to detail, strong collaboration and communication skills, analytical problem-solving abilities, consistency, and self-motivation are essential qualities we seek in our team members. At Alphawave Semi, we offer a flexible work environment that supports personal and professional growth. In addition, we provide a competitive compensation package, Restricted Stock Units (RSUs), opportunities for advanced education from premium institutes, medical insurance, wellness benefits, educational assistance, advance loan assistance, and office lunch & snacks facility. We are committed to promoting diversity and inclusivity, welcoming applicants of all backgrounds and providing accommodations during the recruitment process. If you are passionate about driving innovation in the world of data communication and are eager to work with a dynamic team of talented individuals, we encourage you to apply for the Physical Design Engineer position at Alphawave Semi.,

You are a skilled SOC Verification engineer with over 3 years of experience in the field. Your expertise includes a strong knowledge of ARM architecture, CPU fundamentals, and Cache coherency. You are proficient in programming languages such as C/C++, assembly, and scripting languages. Additionally, you have a good understanding of low-power design and verification methodologies. In this role, you will be responsible for developing CDV UVM verification environments at the system level. You will verify CPU connectivity to IP blocks and develop SoC test plans and test cases. Tracking metrics, including code and functional coverage, will be an essential part of your responsibilities. To qualify for this position, you should hold a Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related field. You must have a minimum of 3 years of experience in SoC ASIC/FPGA verification. Proficiency in SystemVerilog (SV) and Universal Verification Methodology (UVM) is required. Experience with simulation, emulation, and formal verification techniques is also necessary. Strong debugging and problem-solving skills will be beneficial in this role. This position is located in Noida, and the ideal candidate should possess a BTECH/MTECH degree in Electrical/Electronics/Computer Science Engineering or an equivalent field.,

Focus on Connectivity and Network Engineering. Develop competency in your area of expertise and share your expertise by providing guidance and support to others. Interpret clients" needs effectively and complete your role independently or with minimum supervision. Identify problems and relevant issues in straightforward situations and generate effective solutions. Contribute actively in teamwork and maintain good interaction with customers. Design, develop, and maintain Bluetooth protocol stacks and profiles (BT Classic and BLE) for embedded platforms. Work on Bluetooth Audio, LE Audio, and BT Mesh implementations. Integrate Bluetooth features into Linux, Android, or RTOS-based systems. Collaborate closely with cross-functional teams, including hardware, firmware, and application developers. Conduct code reviews, unit testing, and performance optimization. Ensure compliance with Bluetooth SIG standards and actively participate in qualification processes. Debug and resolve complex issues using tools like Ellisys, Frontline, or Wireshark. Required Technical Skills: - Strong programming skills in C/C++, with exposure to Java or Python. - Deep understanding of Bluetooth Core Specification, GATT, L2CAP, HCI, and BT profiles (A2DP, HFP, AVRCP, etc.). - Experience with Bluetooth stack development on Linux/Android platforms. - Familiarity with Bluetooth certification and interoperability testing. - Knowledge of wireless communication protocols and low-power design. Preferred Qualifications: - Bachelor's or Master's degree in Computer Science, Electronics, or related field. - Experience in automotive infotainment, IoT, or wearable devices. - Strong debugging and analytical skills. - Excellent communication and leadership abilities.,

As an Analog Mixed Signal IC Designer with 4-10 years of experience in Bangalore, you will be responsible for designing, implementing, and verifying analog/mixed-signal IC designs for various motion sensor products. Your role will involve mentoring junior engineers in all areas of product design and evaluating system-level trade-offs for next-generation sensor interfaces. Collaborating with the MEMS design team, you will identify IC architectures to meet performance requirements. Additionally, you will interface with digital design engineers to define and optimize sensor architectures and digital signal processing circuits. Providing guidance to layout engineers on physical design and reviewing layouts for optimal design will be part of your responsibilities. Ensuring timely tape-out of designs adhering to required specifications is crucial. You will evaluate and validate designs in the lab, identify any deviations from requirements, and implement corrective actions. Performing any other duties or tasks assigned from time to time is also expected. The ideal candidate should hold a minimum of a Bachelors/Masters in EE with at least 4 years of industry experience in analog or mixed-signal CMOS circuit design. You should have a thorough understanding of analog and mixed-signal systems, micro-architecture trade-offs, and the ability to develop micro-architectures and high-level Matlab system models. A proven track record in designing low-power, low-noise, precision CMOS analog circuits for high-volume manufacturing is essential. Strong skills in designing various analog/mixed-signal blocks such as MEMS sense amplifiers, Bandgap References, Regulators, Charge pumps, ADCs, Oscillator circuits, and PLLs are required. Experience as an IC lead on at least one project with demonstrated success is preferred. Knowledge of design for test approaches and the development of characterization and production test plans is beneficial. Proficiency in lab and test equipment skills for the debug, characterization, and validation of designs is expected. Being diligent, detail-oriented, and proactive in process and flow improvements are qualities that will contribute to your success in this role. Your responsibilities will also involve developing DACs, Headphone, Line, and Speaker drivers, Proprietary Low-Voltage Line Drivers, DC/DC Converters, and various supporting circuitry in advanced CMOS processes. You will participate in all aspects of the design, from concept to production silicon. Involvement in the specification, architectural development, transistor-level design, SPICE, Matlab, and Verilog modeling and simulation, layout supervision, post-layout simulation, chip-level verification, and lab validation is part of the job. Specifically, you will develop PLL and low-jitter filters and gain hands-on experience with Audio CODEC applications and circuits across different CMOS processes and geometry nodes.,

As a Standard Cell Library Developer with 3+ years of relevant experience, you will be responsible for designing and optimizing standard cell libraries that contain logic gates like AND, OR, NAND, NOR, Flip-Flops with various drive strengths and functionality options. You will characterize standard cells by conducting static timing analysis (STA) to evaluate delay, power consumption, and other performance metrics under different process corners and operating conditions. Custom cell design will be required to create specialized standard cells for unique design requirements. Your role will involve generating physical layouts for standard cells using layout design tools such as Cadence Virtuoso and Synopsys IC Compiler. Running design rule checking (DRC) and layout versus schematic (LVS) verification will be essential to ensure that standard cell layouts comply with manufacturing design rules and match their schematics. Additionally, you will be responsible for characterizing and validating standard cell libraries for various technology nodes, ensuring consistency and accuracy. Implementing low-power standard cells with features like power gating and voltage scaling to optimize power consumption will be part of your responsibilities. You will need to address challenges specific to advanced process nodes like FinFET and multi-patterning when designing and optimizing standard cells. Collaboration with manufacturing teams will be necessary to guarantee that standard cell layouts are manufacturable, considering lithography, process variation, and yield. Maintaining detailed documentation of standard cell libraries, including timing models, power models, and layout guidelines, will be crucial. Your role will also involve working with digital design teams to integrate standard cell libraries into the overall chip design, ensuring seamless functionality and compatibility.,

As a Senior Member of Technical Staff (SMTS) Silicon Design Engineer at AMD, you will be an integral part of the Circuit Technology team, focusing on DFT Methodology/Architect/RTL execution for high-speed SERDES Phys, Next-gen Memory Phys, and Die-to-Die interconnect IPs. Your responsibilities will include defining the DFX architecture for high-speed PHYs and die-to-die connectivity IP designs, RTL coding, supporting scan stitching, developing timing constraints, assisting with ATPG, and post-silicon bringup. Join a dynamic team that delivers cutting-edge IPs crucial for every SOC developed by AMD. The ideal candidate possesses strong analytical and problem-solving skills with keen attention to detail. You must demonstrate the ability to work hands-on, be a self-starter, a leader, and independently drive tasks to completion. Key Responsibilities: - Lead and define Design for Test/Debug/Yield Features specific to PHYs. - Implement DFX features into RTL using Verilog. - Comprehend DFX Architectures and micro-architectures. - Utilize JTAG (1149.1/1687/1500)/IJTAG, Scan Compression (EDT, SSH), and at-speed scan testing implementation. - Conduct gate-level simulation using Synopsys VCS and Verdi. - Perform Spyglass bringup and analysis for scan readiness/test coverage gaps. - Plan, implement, and verify MBIST. - Assist Test Engineering in planning, patterns, and debug. - Support silicon bring-up and debug. - Develop efficient DFx flows and methodology compatible with front-end and physical design flows. Preferred Experience: - Proficiency in industry-standard ATPG and DFx insertion CAD tools. - Familiarity with industry-standard DFX methodology: e.g., Streaming Scan Network (SSN), IJTAG, ICL/PDL, etc. - Knowledge of SystemVerilog and UVM. - Expertise in RTL coding for DFx logic, including lock-up latches, clock gates, and scan anchors. - Understanding of low-power design flows such as power gating, multi-Vt, and voltage scaling. - Strong grasp of high-performance, low-power design fundamentals. - Familiarity with fault models including Stuck-at, Transition, Gate-Exhaustive, Path Delay, IDDQ, and Cell Aware. - Exposure to post-silicon testing and tester pattern debug is advantageous. - Excellent problem-solving and debug skills across various design hierarchies. Academic Credentials: - BS/MS/PhD in EE/ECE/CE/CS with industry experience in advanced DFx techniques. Join AMD and be a part of a culture that values innovation, problem-solving, and collaboration. Together, we can advance technology and shape the future of computing.,