Std. Cell/ Layout Engineers Digicomm Semiconductor

3.0 - 7.0 years

0 Lacs

karnataka

On-site

As a Standard Cell Library Developer with 3+ years of relevant experience, you will be responsible for designing and optimizing standard cell libraries that contain logic gates like AND, OR, NAND, NOR, Flip-Flops with various drive strengths and functionality options. You will characterize standard cells by conducting static timing analysis (STA) to evaluate delay, power consumption, and other performance metrics under different process corners and operating conditions. Custom cell design will be required to create specialized standard cells for unique design requirements. Your role will involve generating physical layouts for standard cells using layout design tools such as Cadence Virtuoso and Synopsys IC Compiler. Running design rule checking (DRC) and layout versus schematic (LVS) verification will be essential to ensure that standard cell layouts comply with manufacturing design rules and match their schematics. Additionally, you will be responsible for characterizing and validating standard cell libraries for various technology nodes, ensuring consistency and accuracy. Implementing low-power standard cells with features like power gating and voltage scaling to optimize power consumption will be part of your responsibilities. You will need to address challenges specific to advanced process nodes like FinFET and multi-patterning when designing and optimizing standard cells. Collaboration with manufacturing teams will be necessary to guarantee that standard cell layouts are manufacturable, considering lithography, process variation, and yield. Maintaining detailed documentation of standard cell libraries, including timing models, power models, and layout guidelines, will be crucial. Your role will also involve working with digital design teams to integrate standard cell libraries into the overall chip design, ensuring seamless functionality and compatibility.,

Posted 3 days ago

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Senior DFX Engineer Advanced Micro Devices, Inc

5.0 - 9.0 years

0 Lacs

karnataka

On-site

As a Senior Member of Technical Staff (SMTS) Silicon Design Engineer at AMD, you will be an integral part of the Circuit Technology team, focusing on DFT Methodology/Architect/RTL execution for high-speed SERDES Phys, Next-gen Memory Phys, and Die-to-Die interconnect IPs. Your responsibilities will include defining the DFX architecture for high-speed PHYs and die-to-die connectivity IP designs, RTL coding, supporting scan stitching, developing timing constraints, assisting with ATPG, and post-silicon bringup. Join a dynamic team that delivers cutting-edge IPs crucial for every SOC developed by AMD. The ideal candidate possesses strong analytical and problem-solving skills with keen attention to detail. You must demonstrate the ability to work hands-on, be a self-starter, a leader, and independently drive tasks to completion. Key Responsibilities: - Lead and define Design for Test/Debug/Yield Features specific to PHYs. - Implement DFX features into RTL using Verilog. - Comprehend DFX Architectures and micro-architectures. - Utilize JTAG (1149.1/1687/1500)/IJTAG, Scan Compression (EDT, SSH), and at-speed scan testing implementation. - Conduct gate-level simulation using Synopsys VCS and Verdi. - Perform Spyglass bringup and analysis for scan readiness/test coverage gaps. - Plan, implement, and verify MBIST. - Assist Test Engineering in planning, patterns, and debug. - Support silicon bring-up and debug. - Develop efficient DFx flows and methodology compatible with front-end and physical design flows. Preferred Experience: - Proficiency in industry-standard ATPG and DFx insertion CAD tools. - Familiarity with industry-standard DFX methodology: e.g., Streaming Scan Network (SSN), IJTAG, ICL/PDL, etc. - Knowledge of SystemVerilog and UVM. - Expertise in RTL coding for DFx logic, including lock-up latches, clock gates, and scan anchors. - Understanding of low-power design flows such as power gating, multi-Vt, and voltage scaling. - Strong grasp of high-performance, low-power design fundamentals. - Familiarity with fault models including Stuck-at, Transition, Gate-Exhaustive, Path Delay, IDDQ, and Cell Aware. - Exposure to post-silicon testing and tester pattern debug is advantageous. - Excellent problem-solving and debug skills across various design hierarchies. Academic Credentials: - BS/MS/PhD in EE/ECE/CE/CS with industry experience in advanced DFx techniques. Join AMD and be a part of a culture that values innovation, problem-solving, and collaboration. Together, we can advance technology and shape the future of computing.,

Posted 6 days ago

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