Lead Verification Engineer-Low Power

As a Lead Verification Engineer, you will be responsible for developing and executing comprehensive verification strategies for USB/LPDDR subsystem designs, focusing on low-power design requirements. Your key responsibilities will include: - Collaborating with cross-functional teams to define verification goals and ensure alignment with project objectives. - Designing and implementing reusable, scalable, and efficient verification testbenches using SystemVerilog/UVM or C based, leveraging Cadence VIP and other verification IPs. - Applying expertise in low-power design and verification techniques to ensure accurate and reliable verification of power management features, such as power states, power domains, and power-aware verification methodologies. Qualifications required for this role include: - Extensive experience (8+ years) in verification. - Strong knowledge of Cadence VIP and verification methodologies (SystemVerilog/UVM). - Proficiency in low-power design techniques and power-aware verification methodologies. - Hands-on experience with industry-standard simulation and verification tools (e.g., Cadence Incisive, Synopsys VCS, Mentor Questa). - Solid understanding of verification languages (SystemVerilog, VHDL) and scripting languages (Perl, Python, TCL). - Familiarity with industry standards and protocols related to USB (USB 2.0, USB 3.x) and LPDDR (LPDDR4, LPDDR5). In addition to the technical requirements, this position falls under the job category of VLSI (Silicon engineering) and is a full-time role based in Bangalore, India.,