11 Verification Tools Jobs

Qualcomm India Private Limited is seeking a Layout Engineer to develop block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. In this role, you will utilize your understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. You will conduct analyses, tests, and verify designs using various tools and techniques to identify and troubleshoot issues, while staying updated on new verification methods. Collaborating with multiple internal and external stakeholders, you will align on projects, provide updates, and resolve issues. The ideal candidate should have a Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or a related field with 2+ years of experience in designing custom layouts in relevant domains such as analog, mixed signal, RF, or digital design. Alternatively, an Associate's degree with 4+ years of experience or a High School diploma with 6+ years of experience in custom layout design is also acceptable. Additionally, a minimum of 2 years of experience using layout design and verification tools such as Cadence, LVS, rmap is required. Qualcomm is a company focused on innovation in the CPU market and is looking for a skilled SRAM Mask Layout Designer to join their high-performance CPU team. As an SRAM Mask Layout Designer, you will be responsible for developing block or macro level layouts and floorplans for high-performance custom memories based on project requirements and design schematics. The minimum qualifications for this role include 5+ years of experience with a high school diploma or equivalent, or 5+ years of experience with a BS in Electrical Engineering, or 3+ years of experience with an MS in Electrical Engineering. Direct experience with custom SRAM layout, familiarity with industry-standard custom design tools and flows, knowledge of leading-edge FinFET and/or nanosheet processes, and experience in layout design of library cells, datapaths, and memories in deep sub-micron technologies are preferred qualifications. Key responsibilities of the SRAM Mask Layout Designer include designing layouts for custom memories and digital circuits, interpreting design rule manuals for optimal layout creation, owning the entire layout process from floorplanning to physical verification, using industry-standard verification tools, providing layout fixes as needed, and collaborating with different teams to accurately describe issues and ensure completion. Applicants interested in this position at Qualcomm are encouraged to apply, as Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. For more information about this role, interested individuals can contact Qualcomm Careers directly.,

Qualcomm India Private Limited is seeking a Layout Engineer to develop block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. As a Layout Engineer, you will apply your understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. You will conduct analyses, tests, and verify designs using different tools and techniques to identify and troubleshoot issues, staying abreast of new verification methods. Collaboration with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues will be a key aspect of this role. The ideal candidate should possess a Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or a related field, with at least 2+ years of experience in designing custom layouts in a relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. Alternatively, an Associate's degree in Computer Science, Mathematics, Electrical Engineering, or a related field, with 4+ years of relevant experience, or a High School diploma or equivalent, with 6+ years of relevant experience will also be considered. Candidates should have 2+ years of experience using layout design and verification tools such as Cadence, LVS, and rmap. Additionally, 2-5 years of experience in Custom layout and Memory Layout design, including Memory Leafcell layout library design from scratch, top-level integration, knowledge of different memory architectures and compilers, optimized layout design for better performance, and expertise in Finfet technology and DRC limitations are desired. Proficiency in physical verification flow & debug, including DRC, LVS, ERC, Boundary conditions, Cadence Virtuoso layout editor, Calibre physical verification flow, SKILL, and PERL for custom tiling and automations is expected. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, please reach out to disability-accommodations@qualcomm.com. Qualcomm expects its employees to comply with all applicable policies and procedures, including security and confidentiality requirements. Please note that Qualcomm does not accept unsolicited resumes or applications from agencies. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use Qualcomm's Careers Site. For more information about this role, please contact Qualcomm Careers.,

Responsibilities: Develop and implement comprehensive verification plans utilizing industry-leading methodologies (UVM, Formal Verification) Design and create high-quality verification environments (testbenches) to achieve exceptional code coverage Utilize advanced verification tools (simulators, formal verification tools) to thoroughly verify RTL functionality Debug and analyze verification failures with a keen eye to identify and resolve the root cause of design issues Collaborate effectively with RTL design engineers to ensure efficient bug resolution and verification plan adherence Lead and mentor junior DV engineers within the team, fostering a collaborative and knowledge-sharing environment Participate in code reviews and champion best practices for verification code quality Stay current with the latest advancements in verification tools and methodologies Show more Show less

As a Staff Engineer - Design Verification at Micron Technology, you will be part of a highly innovative and motivated design team working on cutting-edge memory technologies to develop advanced DRAM and Emerging memory products. Your role will involve verifying high density memory chips with complex circuit capabilities, ultra-high-speed designs, and next-generation DDR/LPDDR technologies. You will collaborate with various design and verification teams globally to ensure the successful completion of design projects. Your responsibilities will include: - Taking ownership of verification and conducting end-to-end analysis of complex block-level custom designs for DDR4, LPDDR4, DDR5, and LPDDR5 memory architectures operating at high speeds. - Guiding and directing the verification effort for all projects undertaken by the team. - Providing verification support by simulating, analyzing, and debugging pre-silicon block level/full chip designs. - Developing test cases and stimulus to enhance functional coverage for DRAM and emerging memory products. - Creating and maintaining test benches and test vectors using simulation tools, running regressions for coverage analysis, and collaborating with international colleagues to develop new verification flows. - Contributing to the development of verification methodologies and environments for advanced DRAM and emerging memory products. - Demonstrating a good understanding of digital/mixed-signal circuits and experience in digital/mixed-signal verification. - Utilizing tools like Virtuoso, Xcellium, Simvision, vsim, Waveview, Finseim, and Hspice. - Writing Verilog and Real Number Models, as well as building SV testbenches at block and full-chip levels. - Implementing SV and UVM-based verification, with proficiency in scripting using Perl and Python. - Having previous experience in DRAM memory-related fields is advantageous, along with possessing strong communication, debugging skills, and the ability to work effectively in a team. To qualify for this role, you must hold a Bachelor's or Post Graduate Degree in Electronics Engineering or a related field, with 5-15 years of relevant experience. Micron Technology, Inc. is a global leader in memory and storage solutions, driving innovations that enhance the way information is used to enrich life for all. With a focus on customer satisfaction, technology leadership, and operational excellence, Micron offers a range of high-performance DRAM, NAND, and NOR memory and storage products through its Micron and Crucial brands. The advancements made by Micron's team members contribute to the data economy, enabling progress in artificial intelligence and 5G applications across various platforms. For more information, please visit micron.com/careers. If you require assistance during the application process or need accommodations, please contact hrsupport_in@micron.com. Micron Technology strictly prohibits the use of child labor and complies with all relevant laws, regulations, and international labor standards.,

You will be joining NVIDIA as a Senior Power Verification Engineer, where you will be responsible for verifying the design and implementation of low power features for Smart-NICs and DPUs. These cutting-edge networking processors aim to accelerate network performance, reduce CPU overhead in IP packet transport, and optimize processor cycles for running applications efficiently. The Networking Chip Design team in India is rapidly expanding, offering an exciting opportunity to work on innovative projects in a fast-paced environment. Your key responsibilities will include working on structural and functional verification of low power aspects of NVIDIA's smartNICs and DPUs. You will develop test plans, coverage plans, and test cases, along with test bench components like assertions and coverage points. Collaborating with system and unit level teams, you will ensure comprehensive coverage of features from various aspects such as functional, electrical, performance, and noise. Additionally, you will analyze power consumption by unit IPs through debugging waves and work closely with cross-functional teams to achieve verification convergence. To qualify for this role, you should have a BS/MS or equivalent experience specializing in Low Power techniques and Verification, along with at least 5 years of relevant experience. A strong understanding of power basics, power intent formats, and experience with power check and verification tools is essential. Familiarity with low power design techniques and verification environments will be advantageous for this position. To distinguish yourself as a candidate, prior experience with SmartNICs or high-speed interconnects, proficiency in programming languages such as Python, Perl, or C++, and strong problem-solving skills will be beneficial. Demonstrating good interpersonal skills and a collaborative mindset to work effectively as part of a team will set you apart in this role. NVIDIA is recognized as one of the most sought-after employers in the technology industry, offering competitive salaries and a comprehensive benefits package. As you consider your career growth, explore the opportunities and benefits NVIDIA provides for you and your family at www.nvidiabenefits.com.,

Eridu AI India Private Limited, a wholly owned subsidiary of Eridu Corporation, Saratoga, California, USA, is looking to hire highly motivated and talented professionals for its R&D center in Bengaluru to join our world-class team. Eridu AI is a Silicon Valley hardware startup focused on accelerating training and inference performance for large AI models. Today's AI model performance is often gated by infrastructure bottlenecks. Eridu AI introduces multiple industry-first innovations across semiconductors, software, and systems to deliver solutions that improve AI data center performance to increase GPU utilization while simultaneously reducing capex and power. Eridu AI's solution and value proposition have been widely validated with several hyperscalers. The company is led by a veteran team of Silicon Valley executives and engineers with decades of experience in state-of-the-art semiconductors, optics, software, and systems. We are seeking an RTL Packet Processing Engineer to help define and implement our industry-leading Networking IC. If you're a highly motivated self-starter eager to solve real-world problems, this is a unique opportunity to shape the future of AI Networking. As part of the Design Group, you will be responsible for defining, specifying, architecting, executing, and productizing cutting-edge Networking devices. Responsibilities include Packet Processing Design, Implementation and Testing, Performance Optimization, Protocol Support, and Troubleshooting and Debugging. The ideal candidate should have ME/BE with a minimum of 8-15 years of experience, working knowledge of system Verilog and Verilog, proven expertise in designing and optimizing packet pipelining and QoS mechanisms for high-speed networking devices, solid understanding of ASIC design methodologies, experience with Ethernet/PCIe networking protocols, strong analytical and problem-solving abilities, as well as excellent verbal and written communication skills. At Eridu AI, you'll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI networking solutions, transforming data center capabilities. The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles.,

As a RTL Packet Processing Engineer at Eridu AI India Private Limited, a subsidiary of Eridu Corporation based in Saratoga, California, USA, you will play a crucial role in defining and implementing industry-leading Networking IC. Your primary responsibility will be to design and architect solutions for high-speed networking devices with a focus on latency optimization, quality of service (QoS) support, CAMs, and routing tables. By implementing designs on ASIC platforms, ensuring compliance with industry standards and performance benchmarks, and conducting thorough testing and validation, you will contribute to the development of cutting-edge Networking devices. Your role will involve analyzing and optimizing pipelining architectures to enhance performance metrics, providing support for various networking protocols and standards related to input and output queues, including Ethernet, and troubleshooting and resolving complex issues related to packet queuing. Collaboration with cross-functional teams, including hardware engineers, firmware developers, and system architects, will be essential to investigate and address networking challenges effectively. To qualify for this position, you should hold a ME/BE degree with a minimum of 8-15 years of experience, possess working knowledge of system Verilog and Verilog, and demonstrate prior experience with ownership of memory subsystems. Your expertise in designing and optimizing packet pipelining and QoS mechanisms, familiarity with ASIC design methodologies, simulation, and verification tools, and experience with Ethernet/PCIe networking protocols will be crucial. Strong analytical and problem-solving abilities, attention to detail in troubleshooting and debugging, and effective communication skills will enable you to collaborate efficiently in a team environment and present technical information to diverse audiences. Joining Eridu AI will offer you the opportunity to contribute to the future of AI infrastructure, working alongside a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI networking solutions, transforming data center capabilities. The starting base salary for this role will be determined based on your skills, experience, qualifications, work location, market trends, and compensation of employees in comparable roles.,

We are looking for a highly skilled and experienced Memory Layout Engineer to join our team. As a Memory Layout Engineer, you will be responsible for designing and integrating layouts for advanced memory blocks across leading-edge process technologies. Your role will involve developing and verifying memory compilers with a strong focus on ultra-deep sub-micron layout challenges. Key Responsibilities: Memory Building Block Layout Design: - Designing layouts for essential memory components including Control and Digital logic, Sense amplifiers, Bit-cell arrays, and Decoders. Process Technology Expertise: - Working with advanced process nodes such as 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, and FinFET technologies. Physical Verification: - Developing memory compilers, addressing layout-related issues, and ensuring optimization. - Proficiency in Routing Congestion, Physical Verification in Custom Layout. - Knowledge of verification checks like DRC, LVS, ERC, Antenna, LPE, DFM, etc. - Understanding of analog layout techniques and circuit principles affected by layouts. Tools Experience: - Hands-on experience with industry-standard layout and verification tools in a Linux environment, including Cadence and Mentor EDA tools. Proficiency in VirtuosoXL. Leadership and Communication: - Demonstrated leadership skills to mentor and guide team members in layout execution. - Excellent communication skills and proactive work approach. Qualifications: - BTECH/MTECH - Minimum 3+ years of experience Location: - Bangalore / Hyderabad / Noida This role presents an exciting opportunity to work with cutting-edge technologies and collaborate with a team of experts. If you are passionate about memory layout design and enjoy working in an innovative environment, we encourage you to apply.,

In your new role you will: Be in continuous and intensive contact with our development sites worldwide Advise and support the experts from our business units in verification projects Drive the internal exchange of know-how and experience at Infineon Work out optimization opportunities in the area of verification methodology and verification coverage through integrating the results achieved into Infineons design system and supporting their implementation in the development of new products Collaborate with other disciplines (e.g. Application Engineering) to define the verification methodology and the verification plan Design and develop the verification environment for ICs using the Universal Verification Methodology (UVM) Independently identify sub-modules that are particularly suitable for Formal Verification and apply this methodology Implement test scenarios using System Verilog and verify functionality using a Constrained Random Approach Use the Unified Power Format (UPF) to verify the low-power aspects of our designs You are best equipped for for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.

Defining and developing ASIC RTL verification at both chip and block levels. Creating and executing verification plans for complex digital designs, particularly focusing on PCIe/CXL protocols. Collaborating with cross-functional teams to ensure seamless integration and functionality of designs. Utilizing advanced verification methodologies and tools to achieve high-quality results. Mentoring and guiding junior engineers, promoting best practices, and fostering a culture of continuous improvement. Communicating with internal and external stakeholders to align on project goals and deliverables. The Impact You Will Have: Enhancing the reliability and performance of Synopsys digital verification processes. Improving time-to-market for robust Synopsys Interface IP controller through efficient verification methodologies. Mentoring and nurturing a highly skilled verification team, elevating overall project quality. Influencing strategic decisions that shape the future of Synopsys capabilities. Ensuring that Synopsys remains a leader in the semiconductor industry through continuous technological advancements. What You'll Need: Extensive experience in ASIC RTL verification. In-depth knowledge of PCIe, CXL , UCIe and similar IO protocols. Proficiency in advanced digital design verification tools and methodologies. Strong problem-solving skills and the ability to work independently. Excellent communication skills for effective collaboration with diverse teams. Experience of 18+ years in relevant domain.

Working with Synopsys customers to understand their needs and define verification scope and activities. Understanding the complexity and requirements of verification and proposing resource requirements to complete the activities. Leading a team of engineers to perform various pre-silicon verification activities on IPs/Subsystems. Anticipating problems and risks and working towards a resolution and risk mitigation plan. Assisting and mentoring the team in day-to-day activities and growing the capabilities of the verification team for future assignments. Reviewing various results and reports to provide continuous feedback to the team and improve the quality of deliverables. Reporting status to management and providing suggestions to resolve any issues that may impact execution. Collaborating with architects, designers, and pre and post-silicon verification teams to accomplish your tasks. Adhering to quality standards and good test and verification practices. Ramping up on new Verification tools and methodologies using Synopsys Products to enable customers. Working with other Synopsys teams including BU AEs and Sales to develop, broaden, and deploy Tool and IP solutions. The Impact You Will Have: Driving the success of customer projects by ensuring robust and thorough verification of SoC designs. Enhancing Synopsys reputation as a leader in verification through high-quality deliverables and customer satisfaction. Mentoring and growing the verification team, building a strong foundation for future projects. Identifying and mitigating risks early, ensuring smooth project execution and delivery. Improving verification methodologies and practices, contributing to the overall efficiency and effectiveness of the team. Collaborating with cross-functional teams to achieve seamless integration and execution of verification activities. Providing valuable feedback and insights that drive continuous improvement in verification processes and tools. What You ll Need: B.E/B. Tech/M.E/M. Tech in electronics with a minimum of 12+ years experience in SoC/IP/Subsystems verification domain. Technical expertise in various aspects of pre-silicon Verification (UVM, Coverage Analysis, Verification plan creation, debugging, etc). Good knowledge of various protocols (PCIe, Ethernet, USB, DDR, etc) and/or processor/interconnect/debug architecture. Hands-on experience with verification tools such as VCS, waveform analyzers, and third-party VIP integration (such as Synopsys VIPs). Ability to lead a team to perform verification on complex SoC/IP/Subsystems. Experience with planning and managing verification activities for SoC/Subsystems/IPs. Strong understanding of design concepts, ASIC flows, and stakeholders. Good communication skills.