Verification Engineer

What You Will Be Doing

• Responsible for planning, verification and coverage closures of RTL mainly dealing with Traffic/Buffer Management in Ethernet Switch/Router, based on UVM methodology
• Identification and creation of functional coverage and following the coverage driven methodology
• Work closely with the design team and verification teams to close any assigned tasks
• Understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design
• Collaborate with the emulation, post-silicon & SW teams on a need to basis
• AI based verification flow improvements and automation
  

What We Are Looking For

• B.E./B.Tech with 12+ years OR M.E/M.Tech with 10+ years of relevant experience
• Expertise in Block, sub-system and top level verification & simulation optimizations
• Expertise in DV methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug
• Experience in scripting like perl/python/shell
• Experience with AI based verification flow/automation developments/improvements
• Experience in Gate level simulations with SDF annotation
• Self-motivated person with strong Background in planning, developing and working in functional coverage based constrained random verification environments
  

What Will Make You Stand Out

• Networking fundamentals - switch/router basics
• Buffer management concepts - scheduling concepts, congestion, linked list, different memory organizations
• Strong Interpersonal and communication skills
• Experience of being part of a complete life cycle of the IP verification process - System specification to sign off
• Experience in verifying complex verification environments with complex, cycle accurate checkers.
• Experience with AI based automation of verification flows