92 Vmm Jobs

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Job duties include: Develop Test plans for all features for Block/Core/SOC and Write Functional coverage for these features. Architect and develop scalable and re-usable testbenches, using the framework of the verification methodology Build pseudo-random tests to verify and get to full Functional coverage Debug Regression failures, analyze Functional Coverage gaps and improve tests to cover the gaps Think differently and out-of-the-box to stress the DUT and verify it in an efficient way. Lead the documentation of verification strategy including Test plans, Verification Environment, pseudo-random tests, etc. Lead reviews with design/architecture. Drive improvements in Verification in terms of quality and efficiency. Requirements: Bachelors degree in Electrical Engineering or related degree and 8+ years related experience or Masters degree in Electrical Engineering or related degree and 6+ years related experience 6+ Years of experience writing and debugging complex test benches Must have deep understand of all aspects of Verification from building Testbenches, developing Test plans and pseudo-random tests, Functional coverage. Must have proficiency in System Verilog and Verification Methodologies like UVM/VMM/OVM Should have exceptionally good command over fundamental OOP principles. A good understanding of a complex protocol like PCIe or other multi-layered protocol Capability to work independently and deliver. Knowledge of PCI Express protocol is desired Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law. If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Job duties include: Develop Test plans for all features for Block/Core/SOC and Write Functional coverage for these features. Architect and develop scalable and re-usable testbenches, using the framework of the verification methodology Build pseudo-random tests to verify and get to full Functional coverage Debug Regression failures, analyze Functional Coverage gaps and improve tests to cover the gaps Think differently and out-of-the-box to stress the DUT and verify it in an efficient way. Lead the documentation of verification strategy including Test plans, Verification Environment, pseudo-random tests, etc. Lead reviews with design/architecture. Drive improvements in Verification in terms of quality and efficiency. Requirements: Bachelors degree in Electrical Engineering or related degree and 8+ years related experience or Masters degree in Electrical Engineering or related degree and 6+ years related experience 6+ Years of experience writing and debugging complex test benches Must have deep understand of all aspects of Verification from building Testbenches, developing Test plans and pseudo-random tests, Functional coverage. Must have proficiency in System Verilog and Verification Methodologies like UVM/VMM/OVM Should have exceptionally good command over fundamental OOP principles. A good understanding of a complex protocol like PCIe or other multi-layered protocol Capability to work independently and deliver. Knowledge of PCI Express protocol is desired Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law. If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Job Specs : Expertise in Digital Verification Expertise in Functional Verification Expertise in SOC / IP Verification Expertise in working on system Verilog assertions & test benches Expertise in working on OVM / UVM / VMM based verification flow Expertise in working on ARM processor Expertise in working on AMBA bus protocols (AXI, AHB, APB) Expertise in CXL or PCIe Protocol Verification Expertise in simulation tools (VCS, ModelSim, Questa) Expertise in driving Verification Strategy, writing Test Plan, developing Test Bench, Test cases. Expertise in analysing Code Coverage, Functional Coverage and Assertions. Expertise in verification of complex SoCs. Expertise in Test Plan creation and Verification technologies like Code Coverage, Functional coverage, assertion based verification. Expertise in Verification of complex datapath, DSP based ASICs Expertise in MAC Protocol: USB, WiFi , Bluetooth , PCIe is mandatory Good knowledge in gate-level simulation, and Scripting languages like Python, TCL Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Taiwan are the preferred work locations Preferred resources with valid regional work permit.

Desired Profile : Bachelor's / Master's degree in engineering from EEE / E&C Expertise in managing and leading technical teams across different continents Expertise in leading business strategy in the VLSI / Semiconductor Services / foundry business industry Expertise in managing end to end projects including tape outs Must be willing to travel at short notice, relocate as per business needs Must be willing to work onsite (customer premises) as per business needs Expertise in working on any of the following technologies is mandatory : ANALOG MIXED SIGNAL LAYOUT - finfet / high speed / planar technology nodes ANALOG DESIGN - data converter / power management / pll ANALOG VERIFICATION ASIC PHYSICAL DESIGN ASIC RTL DESIGN DFT DESIGN - jtag / mbist / lbist / scan DIGITAL VERIFICATION - OVM / UVM / VMM EDA CAD FLOW - tcl / primetime / design compiler Job Specs : Responsible for meeting delivery, revenue, operational, customer satisfaction targets and team management Hire and manage high caliber technical teams across GCC, ODC and onsite Develop, Drive high quality business / technology strategy and oversee the translation of this strategy into tactical action Uphold the organization's culture and long term missions Liaise and negotiate with various partners around the world to bring in new partnership. Synergize all company's resources and talents for the growth of company's business Oversee all sectors and fields of the business to ensure the company's competitiveness Provide leadership, direction, major decision making and resolution support to operations, projects and staff. Build strategic business partnerships and execute these opportunities through collaboration with external partners Location - Bengaluru,Bhubaneswar,Kolkata,Kochi,Mysuru

You have an exciting opportunity to join a dynamic team as an Android BSP Engineer with 4-15 years of experience. Your role will be based in Pune and Bangalore. **Role Overview:** As an Android BSP Engineer, you will be responsible for: - Having experience in Android BSP / Linux BSP, C, Cpp - Demonstrating a good understanding of Linux device driver and Kernel modules - Possessing knowledge in core OS concepts like Interrupt, Memory management, Paging - Understanding Hypervisor Type 1/2 is required - Having knowledge of Virtio specifications and virtIO BSP Requirement - Understanding HAL BE, FE - Hands-on experience with VMMs like QEMU/crosvm - Working with IPC in Linux - Handling control plane and messages with Unix domain sockets **Qualification Required:** - Proficiency in C, C++ - Experience with QNX/RTOS, HAL FE / BE - Familiarity with Automotive BSP drivers, Bootloader, HyperVisor, Virt IO, VMM If you are passionate about Android BSP and possess the required skills, we encourage you to apply for this position. For any further queries, please reach out to Srishtis@kpit.com.,

POSITION SUMMARY The candidate should have direct and first-hand experience working in managing 4 -10 member engineering team – and servicing clients in Project (ODC) based execution model as well as Staffing (Hyderabad Onsite requirements). ROLE & RESPONSIBILITIES Incumbent will be responsible for Architecting Verification Environment for ASIC SoC and providing verification support from defining verification plan to various customers products Incumbent will lead of an IP Verification team and provide technical leadership to the Design Verification team as a whole To lead a team of 10-13 engineers Effectively manage team members through coaching and mentoring and provide guidance and career planning to team-members. Must lead management and customer reviews for multiple projects The specification, implementation, and maintenance of an integrated end-to-end formal verification flow for the formal verification objective. Develop/modify scripts to automate the verification process. Maintain and extend assertion libraries, including support for both simulation and FV. Developing verification environment including environment assumptions, assertions, and cover properties in context of the verification plan ESSENTIAL SKILLS & EXPERIENCE Minimum 6 years of experience in System Verilog HVL. Minimum 6 year of experience in OVM/UVM/VMM/Test Harness. Hands on experience of developing assertion, checkers, coverage and scenario creation. Must have executed at-least 2 to 3 SoC Verification projects Experience in developing test and coverage plan, Verification environment and validation plan. Knowledge of at-least one industry standard protocols like Ethernet, PCIe, MIPI, USB or similar is required. Review and Audit participation. At-least 3 years of experience in handling team of 5 to 10 engineers. Define/derive Scope, Estimation, Schedule and Deliverables of proposed work. Assure compatibility of resources, tools, platform Work with customers through acceptance of deliverables. Effectively manage team members through coaching and mentoring and provide guidance and career planning to team-members. Please note that this is a Work from Office Job and incumbent must have willingness and experience of leading and mentoring junior engineers. EDUCATION BACKGROUND B.E./ B.S./ B.Tech/ M.S./ M.Tech in VLSI/Electronics/Electrical/Computer/Instrumentation Engineering.

Description Role : Cisco Network Specialist Experience : 10+ Year relevant in Networking Location : Bangalore / Noida Hybrid Remote 2 days Work from office Shift Timing : 24*7 Rotational Shift – Includes night shifts MUST HAVE Mandatory Skills • 5+ years of relevant experience on with Dell Switches (Hands on) • 8+ years of experience with CISCO Routers & Switches • 10+ years of experience on managing LAN & WAN Infrastructures • 10+ years’ experience on Routing & Switching • Must have Bachelors Degree Highly Preferred Skills: • CISCO ACI & Load Balancing is strongly desired • Preferred knowledge of VELO Cloud (Hands-on) and Wireless • Adaptive, communication, presentation, and leadership skills • Project experience for SDN Infra & Networking Role Responsibilities: • Must have great experience on Routing & Switching & Wireless and Firewalls. • Responsible for the Cisco ACI network architecture component(s) • Must have Palo Alto Experience. • Understand and support Data Centre Networks utilizing Cisco Application Centric Infrastructure and Nexus 9k platforms. • Contribute to the development and performance of a migration plan from traditional data centre network designs to Cisco ACI. • Integrate service appliances to Cisco ACI deployments to include Application Delivery Controllers and Firewalls. • G0od understanding of Inter and Intra Tenant traffic flows, contracts • Experience in L2 outs, L3 outs, VMM integration • Must be expert of routing, switching, wireless, LAN and WAN, i.e. L2 (Wireless IEEE 802.11 a, Ethernet, IEEE 802.1x std. STP, MSTP, RSTP, Dynamic VLAN, HSRP/VRRP.) / L3 (Routing protocols such as EIGRP, OSPF, BGP.), NEXUS, SD-WAN • Ensuring all configurations are in compliance with network standards, reviewing log files, SD-WAN, LAN, WAN, NMS • Participate in the setup, deployment, maintenance, troubleshooting and documentation of enterprise-level, mission-critical, network infrastructure components • Looking to have strong knowledge of SDWAN (Hands-on) and Wireless • Teaming with project managers, cross-functional technology and business teams to ensure successful projects • Owning and documenting escalated support tickets and service requests through resolution via ServiceNow • Adaptive, communication, presentation and leadership skills • Full understanding of WAN/LAN internetworking, protocol interoperability, network architecture development and requirements for testing / proof of concept • Knowledge of Wireless, Nexus, SD-WAN • Working knowledge of Networking products from Cisco, Dell & Extreme Networks • Skills and knowledge and adherence to ITIL & Change Management processes • Excellent communication skills, both written and oral • Strong customer service skills; interfaces with customers, end users, partners and associates • Additionally, the candidate must work well within a team, adapt easily to change, and possess the flexibility to travel. Candidate should have a history of working unsupervised while achieving required goals • Rotating on-call, support queue management, preforming network system analysis and reporting • Willing to work in 24X7 environment

Location- Bommasandra/Jigani. Prefer Aerospace industry, PFD, PDCA/8D methodology, PPAP Level 3, GRR study , SPC, APQP core tools like PFD , FMEA & Control Plan.GD&T. Drawing Specifications , plating, machining, VMM,CMM, Required Candidate profile Location- Bommasandra/Jigani. Prefer Aerospace industry, PFD,PDCA/8D methodology, PPAP Level 3, SPC, APQP core tools like PFD , FMEA Control Plan. GD&T. Machining,

We are seeking experienced Senior/Lead ASIC Verification Engineers to join our Noida-VIP team. With 5 to 15 years of experience in Verification, you will be involved in utilizing industry-standard protocols and methodologies. Your proficiency in System Verilog and Verilog, along with a solid understanding of Object Oriented Programming, will be essential for this role. As a Senior/Lead ASIC Verification Engineer, you will have the opportunity to lead the development of reusable Verification environments for a minimum of 2 projects using VMM, OVM, or UVM methodologies. Your expertise in protocols such as UCIe, PCIe, CXL, Unipro, USB, MIPI, HDMI, Ethernet, DDR, LPDDR, and HBM memory protocol will be valuable. Your responsibilities will include contributing to the development of the VIP, reviewing and signing off on VIP development updates, and collaborating with Architects and methodology experts to address issues and enhance output from an architecture/methodology perspective. If you are a proactive and reliable professional with a passion for Verification, we encourage you to share your updated CV with us at taufiq@synopsys.com or refer individuals who would be interested in this opportunity. At Synopsys, we value and promote Inclusion and Diversity, and we welcome applicants from diverse backgrounds without regard to race, color, religion, national origin, gender, gender identity, age, military veteran status, or disability.,

Designation: - CMM Lab Engineer Contact - 9356395439 Email - jobpune22@gmail.com DME / B. E. CF , Proto part Layout , Part inspection as per drawing. CMM Software (Polyworks), GD & T, Drawing reading,

You should have 7 to 10 years of experience in module level and full chip functional verification. Your responsibilities will include creating test plans, developing test bench, coverage, and GLS. You must possess a minimum of 3 years of experience in System Verilog HVL and a minimum of 3 years of experience in OVM/UVM/VMM/Test Harness. Hands-on experience in developing assertion, checkers, coverage, and scenario creation is essential. It is required that you have executed at least 2 SoC Verification projects and have experience in developing test and coverage plans, Verification environment, and validation plans. Hands-on experience with one industry-standard protocol like Ethernet, PCIe, MIPI, USB, or similar is also necessary. Participation in reviews and audits is expected. Additionally, you should have at least 2 years of experience in handling a team of 5 to 10 engineers. Educational Qualifications: B.E., B.TECH, M.E., M.TECH.,

The Manager, DFT will be responsible for implementing the hardware Memory BIST (MBIST) features that support ATE, in-system test, debug, and diagnostics needs of the memories in design. You will work closely with the design, design-verification, and backend teams to enable the integration and validation of the test logic in all phases of the design and backend implementation flow. The job requires you to have good scripting skills and the ability to design and debug with minimal oversight. You will also be involved in high-quality pattern release to the test team and support silicon bring-up and yield improvement. The ideal candidate for this role should be an ASIC Design DFT engineer with 10+ years of related work experience encompassing a broad mix of technologies. You should have knowledge of the latest state-of-the-art trends in Memory testing and silicon engineering. Hands-on experience in JTAG & IJTAG protocols, MBIST, and scan architectures is essential. Your verification skills should include System Verilog, LEC, and validating test timing of the design. Experience working with gate-level simulations, and debug with VCS and other simulators is required. Understanding the testbench in System Verilog, UVM/VMM is considered an addon. Post-silicon validation and debug experience, along with the ability to work with ATE patterns, is a crucial aspect of this role. Additionally, you should possess strong verbal communication skills and the ability to thrive in a dynamic environment. Proficiency in scripting skills such as Python/Perl is also required for this position.,

As a Verification Engineer at NVIDIA, you will be responsible for verifying the design and implementation of the next generation of PCI Express controllers for GPUs and SOCs. This role offers you the chance to make a real impact in a dynamic, technology-focused company that influences product lines spanning from consumer graphics to self-driving cars and artificial intelligence. Working alongside a global team of exceptional individuals, your mission will be to push the boundaries of what is achievable today and shape the future of computing. At NVIDIA, we are passionate about parallel and visual computing, driven by our shared goal of revolutionizing the use of graphics to solve complex computer science challenges. The evolution of NVIDIA's GPU from a tool for simulating human imagination to a powerhouse for running deep learning algorithms showcases its transformation into the AI computing company. In this role, you will be verifying ASIC design, architecture, golden models, and micro-architecture of PCIE controllers at IP/sub-system levels using advanced verification methodologies like UVM. Your responsibilities will include building reusable bus functional models, monitors, checkers, and scoreboards following a coverage-driven verification approach. Understanding the design specification and implementation, defining verification scope, developing test plans, tests, and verification infrastructure will be key aspects of your role. Collaboration with architects, designers, and pre and post silicon verification teams will be essential to successfully fulfill your responsibilities. To qualify for this position, you should hold a B.Tech./ M.Tech degree or equivalent experience with at least 2 years of relevant experience. Proficiency in verification at Unit/Sub-system/SOC level, expertise in Verilog and SystemVerilog, and comprehensive verification of IP or interconnect protocols (e.g. PCI Express, USB, SATA) are required. Experience in developing functional coverage-based constrained random verification environments, familiarity with DV methodologies like UVM/VMM, and exposure to industry-standard verification tools for simulation and debugging are necessary. To excel in this role, having excellent knowledge of PCIE protocol (Gen3 and above), a solid understanding of system-level architecture for PCIE/CXL-based designs, and experience with scripting languages like Perl, Python, or similar is advantageous. Strong debugging and analytical skills, good interpersonal abilities, and a passion for working collaboratively as part of a team will make you stand out. Join NVIDIA in shaping the future of computing and contribute to groundbreaking technological advancements.,

Job Title: Junior Engineer QA/QC (CMM & Measurement) Location: Tokai Rika Minda India Private Limited, Dabaspete. Department: Quality Assurance / Quality Control Job Description: We are seeking a dedicated and detail-oriented Quality Engineer with strong hands-on experience in precision measurement and drawing interpretation. The ideal candidate will be responsible for maintaining high-quality standards through effective inspection and analysis techniques. Key Responsibilities: Read and interpret engineering drawings with high accuracy and understanding. Measure parts using all types of instruments including: CMM (Coordinate Measuring Machine) VMM (Vision Measuring Machine) Surface Roughness Testers Form Tracers Apply expert knowledge of GD&T (Geometric Dimensioning & Tolerancing) parameters for inspection and documentation. Perform CMM Programming (Mitutoyo CMM experience will be an added advantage). Conduct and understand the basics of Calibration processes and instrument control. Understand and apply GRR (Gage Repeatability & Reproducibility) studies to validate measurement systems. Utilize Statistical Process Control (SPC) methods for continuous monitoring and improvement of production quality. Prepare inspection reports, maintain records, and ensure compliance with company quality standards. Required Skills & Qualifications: Diploma / BE / B.Tech in Mechanical / Industrial / Production Engineering or relevant discipline. 25 years of experience in quality inspection and measurement. Hands-on experience with Mitutoyo or equivalent CMM systems. Sound knowledge in GD&T, SPC, and MSA tools. Familiarity with IATF16949 and ISO standards will be preferred. Strong analytical and problem-solving skills. Preferred Candidate: From an Automotive / Auto-component / Toyota group company background. Proactive attitude and ability to work independently and in a team. Interested candidates can send resumes at manohara.is@trmn.biz

Job Title: ASIC Verification- Sr. Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an accomplished verification engineer with a passion for excellence and a track record of delivering robust, high-quality IP solutions. You thrive in a fast-paced, dynamic environment and are excited by the opportunity to work on next-generation connectivity protocols that power commercial, enterprise, and automotive applications. With a solid foundation in Electrical/Electronics Engineering (BSEE with 2+ years or MSEE with 2+ years of relevant experience), you bring deep expertise in System Verilog and industry-standard verification methodologies such as UVM/OVM/VMM. Your hands-on experience developing HVL-based test environments and extracting meaningful verification metrics sets you apart as a technical leader. You are a collaborative team player who values knowledge sharing and actively contributes to a culture of continuous improvement. Your familiarity with protocols like MIPI-I3C, UFS, AMBA, Ethernet, DDR, PCIe, and USB allows you to quickly ramp up on new projects and deliver results. You bring a strong analytical mindset, exceptional debugging skills, and a drive to meet and exceed quality metrics. Experienced with scripting languages like Perl, TCL, and Python, you automate processes for efficiency and scalability. Your strong communication skills, initiative, and global perspective enable you to work effectively with cross-functional and multi-site teams. Above all, you are a lifelong learner who embraces challenges, adapts to new technologies, and is committed to shaping the future of silicon design. What Youll Be Doing: Specify, architect, and implement advanced verification environments for DesignWare IP cores using System Verilog and state-of-the-art methodologies. Develop and execute comprehensive test plans, ensuring coverage of unit-level and system-level requirements. Design, code, and debug testbenches, test cases, and functional coverage models to validate complex IP functionalities. Perform functional coverage analysis and manage regression testing to achieve and maintain required quality metrics. Collaborate closely with RTL designers and global verification teams to resolve issues and drive verification closure. Leverage scripting (Perl, TCL, Python) to automate verification flows, streamline processes, and enhance productivity. Contribute to the development and refinement of verification methodologies, including VIP development and formal verification approaches. The Impact You Will Have: Ensure the delivery of high-quality, robust IP cores that power critical applications in commercial, enterprise, and automotive markets. Drive innovation in verification methodologies, setting new standards for efficiency and coverage. Enhance time-to-market by identifying and resolving design and verification issues early in the development cycle. Strengthen Synopsys reputation as a leader in silicon IP and verification through technical excellence and customer focus. Mentor and support junior engineers, fostering a culture of learning and continuous improvement. Contribute to the success of global, multi-site R&D teams by providing expertise and driving cross-functional collaboration. What Youll Need: BSEE with 2+ years or MSEE with 2+ years of relevant experience in ASIC or IP verification. Expertise in developing HVL (System Verilog)-based verification environments and testbenches. Strong hands-on experience with industry-standard simulators (VCS, NC, MTI) and debugging tools. Proficiency in verification methodologies such as UVM, OVM, or VMM; exposure to formal verification is highly desirable. Solid understanding of protocols such as MIPI-I3C/UFS/Unipro, AMBA, SD/eMMC, Ethernet, DDR, PCIe, USB. Familiarity with scripting languages (Perl, TCL, Python) and HDLs (Verilog); experience with VIP development is a plus. Demonstrated ability to work with functional coverage-driven methodologies and quality metric goals. Who You Are: Analytical thinker with strong problem-solving and debugging skills. Excellent verbal and written communication abilities. Team player who thrives in collaborative, multi-site environments. Proactive, self-motivated, and able to take initiative on challenging projects. Detail-oriented, quality-focused, and driven by a desire to excel. Adaptable and eager to continuously learn and apply new technologies. The Team Youll Be A Part Of: You will join the Solutions Groups DesignWare IP Verification R&D team, a highly skilled and diverse group of engineers dedicated to delivering world-class IP cores for next-generation connectivity. The team operates in a collaborative, multi-site environment, leveraging global expertise to solve complex verification challenges. Together, you will drive innovation, share knowledge, and uphold Synopsys reputation for technical leadership and excellence. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

NVIDIA is seeking an elite Senior Verification Engineer to verify the design and implementation of the next generation of memory subsystem units for the world's leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA's GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as the AI computing company. What you'll be doing: You will be responsible for verifying the ASIC design, architecture and micro-architecture of memory sub-systems/units using advanced verification methodologies. Understand the design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design. Coming up come up with test plans, tests and verification infrastructure for complex IPs/sub-systems. Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology. Work on advanced verification methodologies like SV/UVM. Perform functional coverage driven verification closure. Working with architects, designers, and pre and post silicon verification teams to accomplish your tasks. What we need to see: B.Tech./ M.Tech., or equivalent experience. 5+ years of relevant experience. Experience in verification of complex IPs/units and sub-systems. Background in verification using random stimulus along with functional coverage and assertion-based verification methodologies. Expertise in Verilog. Knowledge in SystemVerilog or similar HVL / UVM or VMM. Ways to stand out from the crowd: Experience in memory subsystem or network interconnect IP verification. Good debugging and analytical skills with sound scripting knowledge. Good communication and excellent team player. With competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the most desirable employers in the world. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status. #LI-Hybrid

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life's work , to amplify human creativity and intelligence. As an NVIDIAN, you'll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! What you'll be doing: Responsible for verifying the ASIC design, architecture and micro-architecture using advanced verification methodologies. Expected to understand the design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design. Come up with test plans, tests and verification infrastructure for complex IPs/sub-systems. Responsible for performance and deadlock verification of the GPU memory subsystem unit. Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology. Perform functional coverage driven verification closure. Working with architects, designers, and pre and post silicon verification teams to accomplish your tasks. What we need to see: B.Tech./ M.Tech. with 4+ years of relevant experience Experience in verification of complex IPs/units and sub-systems Verification experience using random stimulus along with functional coverage and assertion-based verification methodologies Expertise in Verilog Knowledge in SystemVerilog or similar HVL Familiarity with verification methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug Ways to stand out from the crowd: Experience in memory subsystem or network interconnect IP verification Good debugging and analytical skills Scripting knowledge (Python/Perl/shell) Good communication skills & dream to work as a great teammate With competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the most desirable employers in the world. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status. #LI-Hybrid

You will be joining a team of highly skilled engineers who are responsible for designing and developing cutting-edge routing and optical products using the latest industry tools. As part of your role, you will be involved in the following key responsibilities: - Designing and implementing complex FPGAs. - Participating in the architecture definition, implementation, and verification phases. - Developing detailed design specifications and test plans. - Implementing block-level RTL, performing synthesis, and achieving timing closure. - Collaborating with cross-functional teams including hardware, software, diagnostics, and signal integrity groups. - Assisting in complex subsystem level lab bring-up, integration, and unit test validation. - Contributing to the design process adoption within the team. - Working on improving design, development, and verification methodologies. To be successful in this role, you should possess the following qualifications: - Background in networking and system design. - Experience in designing with Xilinx, Microsemi, and Altera FPGAs. - Proficiency in HDL languages such as Verilog, VHDL, and System Verilog. - Hands-on experience with Ethernet-based protocols, PCIe, AXI, memory controllers, OTN, I2C, SPI, UART, etc. - Familiarity with simulation flows like UVM and VMM is an added advantage. - Knowledge in signal integrity and system bring-up is a plus. - Basic knowledge of Unix systems and scripting tools is beneficial. - Ability to work independently, provide mentorship, and demonstrate strong leadership skills. - Self-motivation, teamwork, and excellent communication skills are essential. Educational Background: Typically requires a minimum of 12 years of experience in FPGA designs with an MTech/BTech in EE/EC domain. #WeAreCisco: At Cisco, every individual contributes their unique skills and perspectives towards our shared purpose of creating an inclusive future for all. Our passion for connection drives us to celebrate diversity and focus on unlocking potential. Cisconians have the opportunity to explore multiple career paths within the company, with a strong emphasis on learning and development at every stage. Our technology, tools, and culture support hybrid work trends, enabling everyone to excel and grow. We recognize the importance of uniting communities, with our employees actively participating in 30 employee resource organizations known as Inclusive Communities. These groups foster belonging, promote learning to become informed allies, and drive positive change. Additionally, dedicated paid time off for volunteering (80 hours per year) allows us to give back to causes we care about, with nearly 86% of Cisconians participating. Driven by our people, our purpose is to lead the way in technology that powers the internet. We help our customers reimagine their applications, secure their enterprise, transform their infrastructure, and achieve sustainability goals. Every action we take is a step towards a more inclusive future for all. Join us on this journey and take your next step to be yourself, with us!,

We are looking for experienced Senior/Lead ASIC Verification Engineers for our Noida-VIP team. Does this sound like a good role for you Experience : 5yrs to 15 years (multiple roles) Location: Noida Associated with Verification especially using industry-standard protocols & methodology Languages: Hands-on experience with System Verilog & Verilog . Should have a good understanding of Object Oriented Programming. Involved & played a driving role in the development of reusable Verification environments for at least 2 verification projects using VMM/OVM/UVM methodologies . Protocol experience: Should have experience on any of the UCIe/PCIe/CXL/Unipro/USB/MIPI/HDMI/Ethernet/DDR/LPDDR/HBM memory protocol Job responsibilities: Able to contribute to the development of the VIP Responsible & can be relied on for review sign-off of VIP development and updates from a technical perspective including methodology and protocol functional prospective. Liaison with Architects/methodology experts to achieve resolutions on issues or driving output from an architecture/methodology perspective Please share your updated CV to [HIDDEN TEXT] or refer who would like to explore this opportunity. Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, gender identity, age, military veteran status, or disability. Show more Show less

Expertise in UVM and System Verilog. Experience in verification IP modeling with knowledge of test case coding, scoreboard design, assertions, checkers & functional coverage. Involved & played a driving role in the development of reusable Verification environments for at least 2 verification projects using VMM/OVM/UVM methodologies. Protocol experience: Should have experience on UCIe / PCIe / CXL / Unipro / USB / MIPI / HDMI / Ethernet / DDR / LPDDR / HBM memory protocol. Job Responsibilities: Able to contribute to the development of the VIP. Responsible & can be relied on for review sign-off of VIP development and updates from a technical perspective including methodology and protocol functional prospective. Liaison with Architects/methodology experts to achieve resolutions on issues or driving output from an architecture/methodology

Expertise in UVM and System Verilog. Experience in verification IP modeling with knowledge of test case coding, scoreboard design, assertions, checkers & functional coverage. Involved & played a driving role in the development of reusable Verification environments for at least 2 verification projects using VMM/OVM/UVM methodologies. Protocol experience: Should have experience on UCIe / PCIe / CXL / Unipro / USB / MIPI / HDMI / Ethernet / DDR / LPDDR / HBM memory protocol. Job Responsibilities: Able to contribute to the development of the VIP. Responsible & can be relied on for review sign-off of VIP development and updates from a technical perspective including methodology and protocol functional prospective. Liaison with Architects/methodology experts to achieve resolutions on issues or driving output from an architecture/methodology

We make real what matters. This is your role. Questa verification IPs help design teams find more bugs in less time than conventional simulation techniques. You will specify, implement, test and enhance these verification components for a wide range of end user applications. You will work on technologies involving SV, UVM, Assertions, Coverage, Test plan, BFM design, debug, and logger. You will get along with TMEs and Field AEs or directly with customers to deploy or resolve customer issues. We dont need superheroes, just super minds. You're an Electronics Engineer (B.Tech/ M.Tech) or related field from a reputed institute You've got phenomenal knowledge of verification engineering and have between 2 - 8 years of working experience as well. You've sound knowhow of System Verilog for test bench with exposure to verification methodologies like UVM, VMM etc. You've intimate knowledge of one or more standard bus protocols, like PCIe, USB, SATA, NVMe, Flash, DIMM etc. You are a great teammate, resilient and sincere, Enjoy learning new things and build knowledge base in new area.

Should have experience in Dimension Calibration Lab. Handling equipment like ULM, FCDM, DCT, VMM etc. Must have experience handling NABL audit independently & ISO/IEC 17025:2017. Experience minimum 3 years.

OPTOMECH ENGINEERS PVT LTD Service Engineer Mechanical -Trainee About Us Optomech Engineers Pvt. Ltd. was founded in Hyderabad, India in the year 1981. Optomech has over 40 years of experience in successful development, manufacturing, servicing and marketing of products involving vision technology for quality inspection. We are closely orientated towards the needs of the market. We are one of the leading providers of Optical and Digital equipments quality inspection. Renowned companies place their trust in the solutions and services provided by Optomech. Our Products: Optical Measuring Equipments such as Optical Profile Projectors , Video Measuring Machines for Precision Engineering industries and Machine Vision Based High Speed Online Inspection Systems for Pharma and FMCG Packaging. Our requirement We are looking for Mechanical Engineering Graduates to work in our company as Service Engineers and be a part of our Sales and Servicing Team. Job Description Final Testing and calibration of our optical measuring range of equipments. Onsite installation and training Aftersales service support online and onsite Maintain and keep calibration masters updated. Maintain and keep up to date equipment installation and operations manuals Prepare installation and operations manuals in digital format Qualification: BE / BTech Mechanical Engineering Experience : One years or more in similar position Competencies: Well versed with MS Office. Knowledge of measuring instruments eg Vernier Calipers , Micrometers , Height Gauge, Optical Profile Projector, Video Measuring Machines , CMM ect Behavioural Adherence to process guidelines Flexible and quick adaptation to new technology coding skills Well organized with good planning skills. Place of Work /Job Location: The job location is at our works at Hyderabad, Telangana. Person should be willing to relocate to Hyderabad immediately. (For out of station persons, company will assist in finding suitable accommodation near our works.) Remuneration: Experience Engineering graduates are paid a starting salary of Rs 2 .4 L pa .CTC during first 3 months training period. Salary will be increased to 2.65 L pa CTC after completion of training. (Note: Higher Salary can be considered for deserving candidates having exposure/ useful experience in working on the subjects mentioned above viz CMM, Video Measuring machines etc. Increments : Will be given Quarterly/annual increments based on companys performance evaluation system. Performance Incentive: In addition there will be performance incentive and awards given from time to time based on the initiatives taken by you on improving your job performance thru innovation and knowledge enhancement.

Description Role : Cisco Network Specialist Experience : 10+ Year relevant in Networking Location : Bangalore / Noida Hybrid Remote 2 days Work from office Shift Timing : 24*7 Rotational Shift – Includes night shifts MUST HAVE Mandatory Skills • 5+ years of relevant experience on with Dell Switches (Hands on) • 8+ years of experience with CISCO Routers & Switches • 10+ years of experience on managing LAN & WAN Infrastructures • 10+ years’ experience on Routing & Switching • Must have Bachelors Degree Highly Preferred Skills: • CISCO ACI & Load Balancing is strongly desired • Preferred knowledge of VELO Cloud (Hands-on) and Wireless • Adaptive, communication, presentation, and leadership skills • Project experience for SDN Infra & Networking Role Responsibilities: • Must have great experience on Routing & Switching & Wireless and Firewalls. • Responsible for the Cisco ACI network architecture component(s) • Must have Palo Alto Experience. • Understand and support Data Centre Networks utilizing Cisco Application Centric Infrastructure and Nexus 9k platforms. • Contribute to the development and performance of a migration plan from traditional data centre network designs to Cisco ACI. • Integrate service appliances to Cisco ACI deployments to include Application Delivery Controllers and Firewalls. • G0od understanding of Inter and Intra Tenant traffic flows, contracts • Experience in L2 outs, L3 outs, VMM integration • Must be expert of routing, switching, wireless, LAN and WAN, i.e. L2 (Wireless IEEE 802.11 a, Ethernet, IEEE 802.1x std. STP, MSTP, RSTP, Dynamic VLAN, HSRP/VRRP.) / L3 (Routing protocols such as EIGRP, OSPF, BGP.), NEXUS, SD-WAN • Ensuring all configurations are in compliance with network standards, reviewing log files, SD-WAN, LAN, WAN, NMS • Participate in the setup, deployment, maintenance, troubleshooting and documentation of enterprise-level, mission-critical, network infrastructure components • Looking to have strong knowledge of SDWAN (Hands-on) and Wireless • Teaming with project managers, cross-functional technology and business teams to ensure successful projects • Owning and documenting escalated support tickets and service requests through resolution via ServiceNow • Adaptive, communication, presentation and leadership skills • Full understanding of WAN/LAN internetworking, protocol interoperability, network architecture development and requirements for testing / proof of concept • Knowledge of Wireless, Nexus, SD-WAN • Working knowledge of Networking products from Cisco, Dell & Extreme Networks • Skills and knowledge and adherence to ITIL & Change Management processes • Excellent communication skills, both written and oral • Strong customer service skills; interfaces with customers, end users, partners and associates • Additionally, the candidate must work well within a team, adapt easily to change, and possess the flexibility to travel. Candidate should have a history of working unsupervised while achieving required goals • Rotating on-call, support queue management, preforming network system analysis and reporting • Willing to work in 24X7 environment