NextSilicon is redefining high-performance computing. Our accelerated compute solutions use intelligent, adaptive algorithms to significantly boost the performance of supercomputers, driving the industry into a new era. Our unique software-defined hardware architecture enables HPC to deliver on its promise of breakthroughs across advanced research fields — from climate science to artificial intelligence. At NextSilicon, our work is guided by three core values: Professionalism : We strive for exceptional results through professionalism and unwavering dedication to quality and performance. Unity : Collaboration is key to success. That's why we foster a work environment where every employee can feel valued and heard. Impact : We're passionate about developing technologies that make a meaningful impact on industries, communities, and individuals worldwide. We are looking for an experienced STA Expert to join our growing BE team. We are working on the most challenging and interesting ASIC chips. Come join us and have a big impact on our groundbreaking and innovative designs. Requirements: BSc/MSc in Electrical Engineering/Computer Science. 8+ years of experience in VLSI backend (RTL2GDS). 5+ years experience in STA (Prime-Time/Signoff). Experience Full chip STA on complex SoCs experience. Expert knowledge and hands-on experience in timing closure & signoff methodologies. Good knowledge of DFT architecture and DFT timing related issues Good knowledge of Async timing concepts & verification. Good knowledge of the full backend flows from RTL to TO. (Synthesis, FP, PnR , CTS , STA, EM/IR, Chip Integration, high-frequency designs) Responsibilities: Take part in STA activities for blocks, Sub Systems and Full chip, from definitions to TO Analyze timing results, verify correctness and provide timing budget for the different partitions. Own the timing constraints both for STA and P&R flow. Working closely with architecture, design, PD and DFT teams to make sure timing closure and ensures product success Identify risks and bottlenecks, work closely with PD, RTL and DFT teams, ensuring convergence throughout various project stages. Participating in design methodology, reviews and tool automation work and definition As part of this rule you will gain very good understanding of our HPC and AI designs and sub system as well as product targets
As a DFT Technical Manager at NextSilicon, you will play a crucial role in the DFT implementation of the company's next SOC. Your primary focus will be on developing and implementing testing methodologies to ensure the functionality, reliability, and manufacturability of integrated circuits (ICs) and other hardware designs. Your responsibilities will include developing DFT flow/methodologies, managing a team of 3-4 DFT engineers, and ensuring thorough testing and fault coverage alignment with industry standards. **Role Overview:** NextSilicon is reimagining high-performance computing with accelerated compute solutions and a software-defined hardware architecture. As a DFT Technical Manager, your role is critical in developing and implementing testing methodologies to ensure the functionality and reliability of integrated circuits and hardware designs. **Key Responsibilities:** - Develop DFT methodologies for IC designs, such as scan chains, built-in self-test (BIST), boundary scan, and MBIST. - Implement and validate DFT features to ensure coverage and quality. - Perform scan insertion, MBIST insertion, and generate ATPG patterns for high coverage. - Collaborate with design teams to create test strategies and plans. - Analyze fault models, optimize for high coverage, and troubleshoot design issues. - Work with cross-functional teams to integrate DFT features effectively and document DFT architecture and procedures. **Qualifications Required:** - Minimum 12 years of experience in DFT implementation/methodology. - Strong understanding of digital design and test principles. - Proficiency in DFT techniques like scan insertion, BIST, and ATPG. - Experience with EDA tools (e.g., Synopsys DFT Compiler, Mentor Tessent) and scripting languages (e.g., Python, TCL). - Knowledge of IC design flows, verification tools, and fault models. - Ability to lead/manage junior DFT engineers and develop flow/methodology for DFT techniques. At NextSilicon, professionalism, unity, and impact are core values that guide our work. We strive for exceptional results, foster collaboration, and are passionate about developing technologies that make a meaningful impact globally. Join us in reimagining high-performance computing and driving breakthroughs in advanced research fields.,