The Rivos Power team is seeking a highly motivated engineer to develop and strategically drive state-of-the-art power modeling and optimization across our CPU and SoC blocks.In this role, you will have the opportunity to work in an innovative, collaborative, and high-growth environment. The ideal candidate will possess in-depth experience in the full spectrum of silicon power reduction. This includes a foundation in solid power analysis, performance benchmarking, and design optimization at all levelsfrom microarchitecture and physical implementation to standard power-performance benchmarking. What You&aposll Do Model and analyze power consumption for various workloads on custom silicon, working closely with the CPU Architecture, Performance, and Implementation teams to define overall power requirements. Analyze power and performance trade-offs, drive detailed cost-benefit analyses, and make recommendations for power reduction strategies. Collaborate with the Performance, Design Verification, and RTL teams to create targeted test vectors that model appropriate workloads and functionality scenarios for accurate simulation. Own the end-to-end power simulation process, including analysis, tuning, correlation, and presenting results to the Architecture, Logic Design, and Physical Design teams. Partner with the CAD and Physical Design teams to enhance power estimation methodologies, simulation flows, and regression analysis. What You&aposll Bring A Bachelor&aposs or Master&aposs degree in EE/EECS with 4-7 years of relevant industry experience. 4 to 7 years of direct experience in power-aware design, including analysis, benchmarking, modeling, and simulation. Strong working knowledge of CPU architectures and workload modeling for power analysis. Familiarity with the RISC-V architecture is a significant plus. Proficiency with Verilog and SystemVerilog RTL coding. Experience with the complete silicon design flow and evaluating power, performance, and area (PPA) trade-offs at the architectural, logic, and circuit levels. Hands-on experience with state-of-the-art EDA tools for gate-level and transistor-level power modeling and simulation. Strong scripting skills in Python, TCL, or other relevant languages. A proven ability to solve problems dynamically, innovate, drive decisions, and lead team efforts to deliver results under aggressive schedules. Show more Show less
Rivos is on a mission to build the best enterprise SOCs in the world with class-leading performance, power, security, and RAS features. We are seeking Memory Controller design verification engineers to join our team in building the best high-performance memory interface in the world. As a memory subsystem design verification engineer, you'll be responsible for all aspects of digital verification such as functional, performance, DFD, and DFT features around DDR and HBM memory subsystem designs. Responsibilities - Work closely with architect and design team to verify the feature sets of the DDR and HBM memory subsystem design. - Collaborate with 3rd party IP vendors to validate the correctness of integration and custom features. - Develop test plan and testbench. - Integrate and bring up VIPs such as DDR_PHY, DDR_Model as part of the testbench. - Create test stimulus, checkers, and scoreboard in SystemVerilog/UVM. - Conduct debugging, regression testing, and coverage closure. - Provide debug support to emulation and silicon-bring up teams. - Capable of working effectively with teams across different continents. Key Qualifications - Hands-on experience in verifying the digital logic portion of DDR/HBM memory subsystem design. - Familiarity with JEDEC specifications of LPDDRx/DDRx/HBMx. - Understanding of the DDR DFI specification and protocol. - Knowledge of Reliability, availability, and serviceability (RAS) features in the context of memory subsystem, including error detection/correction and encryption. Education And Experience - Masters Degree or Bachelors Degree with 3-5 years of experience.,
Positions are open for immediate Co-op/internship(6 months or more duration) in the areas of CPU and SOC verification from unit level to chip level as well as all aspects of verification such as functional, microarchitecture, performance, and formal. We are looking for all levels of talent, from entrance to advanced level of experience. Responsibilities Work closely with architecture and RTL designers on verifying the functionality correctness of the design Reviewing Architecture and Design Specifications Develop test plans and test environments Develop tests in assembly, C/C++, or vectors according to test plans Develop coverage monitors and analyze coverage to ensure all the test cases in the plans are covered Develop checkers in SystemVerilog or C-base transactors to verify the design Write assertions and apply formal verification to the designImplementing test benches, generating directed/constrained random tests Debugging failures, running simulations, tracking bugs Handling schedules and supporting multi-functional engineering effortAssisting in verification flows, automation scripts and regressions Requirements In-depth knowledge of digital logic design, CPU/SOC architecture and microarchitecture. Sophisticated knowledge of SystemVerilog. Experienced level knowledge C/C++.Relevant knowledge of verification methodologies and tools such as simulators, waveform viewers, build and run automation, coverage collection. Basic knowledge of formal verification methodology is a plus. Excellent knowledge of one of the scripting languages such as Python, TCL is a plus. Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated. Ability to work well in a team and be productive under aggressive schedules. Education And Experience PhD, Master’s Degree or Bachelor’s Degree in technical subject area.
Positions are open for immediate Co-op/internship(6 months or more duration) in the areas of CPU and SOC verification from unit level to chip level as well as all aspects of verification such as functional, microarchitecture, performance, and formal. We are looking for all levels of talent, from entrance to advanced level of experience. Responsibilities Work closely with architecture and RTL designers on verifying the functionality correctness of the design Reviewing Architecture and Design Specifications Develop test plans and test environments Develop tests in assembly, C/C++, or vectors according to test plans Develop coverage monitors and analyze coverage to ensure all the test cases in the plans are covered Develop checkers in SystemVerilog or C-base transactors to verify the design Write assertions and apply formal verification to the designImplementing test benches, generating directed/constrained random tests Debugging failures, running simulations, tracking bugs Handling schedules and supporting multi-functional engineering effortAssisting in verification flows, automation scripts and regressions Requirements In-depth knowledge of digital logic design, CPU/SOC architecture and microarchitecture. Sophisticated knowledge of SystemVerilog. Experienced level knowledge C/C++.Relevant knowledge of verification methodologies and tools such as simulators, waveform viewers, build and run automation, coverage collection. Basic knowledge of formal verification methodology is a plus. Excellent knowledge of one of the scripting languages such as Python, TCL is a plus. Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated. Ability to work well in a team and be productive under aggressive schedules. Education And Experience PhD, Masters Degree or Bachelors Degree in technical subject area. Show more Show less