Memory Controller Verification

Rivos is on a mission to build the best enterprise SOCs in the world with class-leading performance, power, security, and RAS features. We are seeking Memory Controller design verification engineers to join our team in building the best high-performance memory interface in the world. As a memory subsystem design verification engineer, you'll be responsible for all aspects of digital verification such as functional, performance, DFD, and DFT features around DDR and HBM memory subsystem designs. Responsibilities - Work closely with architect and design team to verify the feature sets of the DDR and HBM memory subsystem design. - Collaborate with 3rd party IP vendors to validate the correctness of integration and custom features. - Develop test plan and testbench. - Integrate and bring up VIPs such as DDR_PHY, DDR_Model as part of the testbench. - Create test stimulus, checkers, and scoreboard in SystemVerilog/UVM. - Conduct debugging, regression testing, and coverage closure. - Provide debug support to emulation and silicon-bring up teams. - Capable of working effectively with teams across different continents. Key Qualifications - Hands-on experience in verifying the digital logic portion of DDR/HBM memory subsystem design. - Familiarity with JEDEC specifications of LPDDRx/DDRx/HBMx. - Understanding of the DDR DFI specification and protocol. - Knowledge of Reliability, availability, and serviceability (RAS) features in the context of memory subsystem, including error detection/correction and encryption. Education And Experience - Masters Degree or Bachelors Degree with 3-5 years of experience.,