Rivos

Rivos is on a mission to build the best enterprise SOCs in the world with class leading performance, power, security and RAS features. We are seeking Memory Controller design verification engineers to join our team in building the best high performance memory interface in the world. As a memory subsystem design verification engineer, you'll be responsible for all aspects of digital verification such as functional, performance, DFD and DFT features around DDR and HBM memory subsystem designs. Responsibilities Work closely with architect and design team to verify the feature sets of the DDR and HBM memory subsystem design Work closely with 3rd party IP vendors to validate the correctness of integration and custom features. Develop testplan and testbench Integrate and bring up VIPs such as DDR_PHY, DDR_Model as part of testbench Develop test stimulus, checkers and scoreboard in SystemVerilog/UVM Debug, regression and coverage closure Provide debug support to emulation and silicon-bring up teams. Able to work with teams across the continents Key Qualifications Hands-on experience of verifying digital logic portion of DDR/HBM memory subsystem design Knowledge in JEDEC specification of LPDDRx/DDRx/HBMx Knowledge in the DDR DFI specification and protocol Knowledge in Reliability, availability and serviceability (RAS) features in the context of memory subsystem such as Error detection/correction and Encryption Education and Experience Master’s Degree or Bachelor’s Degree with 3-5 years of experience

Rivos is on a mission to build the best enterprise SOCs in the world with class leading performance, power, security and RAS features. We are seeking Memory Controller design verification engineers to join our team in building the best high performance memory interface in the world. As a memory subsystem design verification engineer, youll be responsible for all aspects of digital verification such as functional, performance, DFD and DFT features around DDR and HBM memory subsystem designs. Responsibilities Work closely with architect and design team to verify the feature sets of the DDR and HBM memory subsystem design Work closely with 3rd party IP vendors to validate the correctness of integration and custom features. Develop testplan and testbench Integrate and bring up VIPs such as DDR_PHY, DDR_Model as part of testbench Develop test stimulus, checkers and scoreboard in SystemVerilog/UVM Debug, regression and coverage closure Provide debug support to emulation and silicon-bring up teams. Able to work with teams across the continents Key Qualifications Hands-on experience of verifying digital logic portion of DDR/HBM memory subsystem design Knowledge in JEDEC specification of LPDDRx/DDRx/HBMx Knowledge in the DDR DFI specification and protocol Knowledge in Reliability, availability and serviceability (RAS) features in the context of memory subsystem such as Error detection/correction and Encryption Education and Experience Master s Degree or Bachelor s Degree with 3-5 years of experience

Positions are open for full-time and Co-op/internship in the areas of CPU and SOC verification from unit level to chip level as well as all aspects of verification such as functional, microarchitecture, performance, and formal. We are looking for all levels of talent, from entrance to advanced level of experience. Responsibilities Work closely with architecture and RTL designers on verifying the functionality correctness of the design Reviewing Architecture and Design Specifications Develop test plans and test environments Develop tests in assembly, C/C++, or vectors according to test plans Develop coverage monitors and analyze coverage to ensure all the test cases in the plans are covered Develop checkers in SystemVerilog or C-base transactors to verify the design Write assertions and apply formal verification to the designImplementing test benches, generating directed/constrained random tests Debugging failures, running simulations, tracking bugs Handling schedules and supporting multi-functional engineering effortAssisting in verification flows, automation scripts and regressions Requirements In-depth knowledge of digital logic design, CPU/SOC architecture and microarchitecture. Sophisticated knowledge of SystemVerilog. Experienced level knowledge C/C++.Relevant knowledge of verification methodologies and tools such as simulators, waveform viewers, build and run automation, coverage collection. Basic knowledge of formal verification methodology is a plus. Excellent knowledge of one of the scripting languages such as Python, TCL is a plus. Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated. Ability to work well in a team and be productive under aggressive schedules. Education and Experience PhD, Master’s Degree or Bachelor’s Degree in technical subject area.

Positions are open for full-time and co-op/internship in the areas of CPU and SOC physical implementation from unit level to chip level, involving all aspects of physical design functions such as P&R, timing, floorplan, clocking, electrical analysis, and power. Responsibilities Own block level design from RTL-to-GDSII and drive synthesis, floor-planning, place & route, timing closure, and signoff. Work extensively with Micro-architects to perform feasibility studies and explore performance, power & area (PPA) tradeoffs for design closure. Develop physical design methodologies and customize recipes across various implementation steps to optimize PPA. Work with a multi-functional engineering team to implement and validate physical design by running all signoff flows such as Timing, Power, EM/IR, PDV. Requirements Knowledge using synthesis, place & route, analysis and verification CAD tools. Familiarity with logic & physical design principles to drive low-power & higher-performance designs. Knowledge of scripting in some of these languages: Unix, Perl, Python, and TCL. Good understanding of device physics and experience in deep sub-micron technologiesKnowledge of Verilog and SystemVerilog. Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated. Ability to work well in a team and be productive under aggressive schedules. Education and Experience PhD, Master’s Degree or Bachelor’s Degree in technical subject area.

Positions are open for full-time and co-op/internship in the areas of CPU and SOC physical implementation from unit level to chip level, involving all aspects of physical design functions such as P&R, timing, floorplan, clocking, electrical analysis, and power. Responsibilities Own block level design from RTL-to-GDSII and drive synthesis, floor-planning, place & route, timing closure, and signoff. Work extensively with Micro-architects to perform feasibility studies and explore performance, power & area (PPA) tradeoffs for design closure. Develop physical design methodologies and customize recipes across various implementation steps to optimize PPA. Work with a multi-functional engineering team to implement and validate physical design by running all signoff flows such as Timing, Power, EM/IR, PDV. Requirements Knowledge using synthesis, place & route, analysis and verification CAD tools. Familiarity with logic & physical design principles to drive low-power & higher-performance designs. Knowledge of scripting in some of these languages: Unix, Perl, Python, and TCL. Good understanding of device physics and experience in deep sub-micron technologiesKnowledge of Verilog and SystemVerilog. Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated. Ability to work well in a team and be productive under aggressive schedules. Education and Experience PhD, Master s Degree or Bachelor s Degree in technical subject area.

Positions are open for full-time in the ares of physical design and integration from sub-system level to full chip level, involving all aspects of physical design partition and integration functions. Responsibilities Own sub-system level or full chip level physical design integration, particularly focusing on design partition/integration, pin arrangement, feedthrough creation, clock/power grid planning. Be responsible for design integration and signoff coordination at sub-system or full chip level Evaluate/implementation physical design for channel, particularly for route ability and repeater planning Work with block or sub-system owners across the whole design cycles to drive design closure and design release/integration Participate flow/methodology development with CAD team Requirements Experience in design partitioning, budgeting, pin planning with multiple takeout experience Knowledge using synthesis, place & route, analysis and verification CAD tools. Familiarity with logic & physical design principles to drive low-power & higher-performance designs. Knowledge of scripting in some of these languages: Unix, Perl, Python, and TCL Good understanding of device physics and experience in deep sub-micron technologiesKnowledge of Verilog and SystemVerilog Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated. Ability to work well in a team and be productive under aggressive schedules. Education and Experience PhD, Master s Degree or Bachelor s Degree in technical subject area with more than five years of experience in relevant areas.