Memory Controller Verification

You will be joining Rivos, a company dedicated to building the best enterprise SOCs in the world with class-leading performance, power, security, and RAS features. Specifically, Rivos is looking for Memory Controller design verification engineers to help create the best high-performance memory interface globally. As a memory subsystem design verification engineer at Rivos, your role will involve various aspects of digital verification, including functional, performance, DFD, and DFT features related to DDR and HBM memory subsystem designs. **Responsibilities:** - Collaborate closely with the architect and design team to verify the feature sets of DDR and HBM memory subsystem designs - Coordinate with 3rd party IP vendors to validate the integration and custom features" correctness - Create test plans and test benches - Integrate and initialize VIPs like DDR_PHY and DDR_Model into the test bench - Generate test stimulus, checkers, and scoreboard using SystemVerilog/UVM - Conduct debugging, regression testing, and coverage closure - Offer debug support to emulation and silicon bring-up teams - Capable of collaborating effectively with teams across different continents **Key Qualifications:** - Hands-on experience in verifying the digital logic portion of DDR/HBM memory subsystem designs - Familiarity with JEDEC specifications of LPDDRx/DDRx/HBMx - Understanding of the DDR DFI specification and protocol - Knowledge of Reliability, Availability, and Serviceability (RAS) features in memory subsystems such as error detection/correction and encryption If additional company details were provided in the job description, they would be mentioned here. However, as no such information was included, this section is omitted. **Education And Experience:** - Masters Degree or Bachelors Degree with 3-5 years of experience,