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CAPRUS IT PRIVATE LIMITED
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ASIC/RTL Design Engineer - SoC

ASIC/RTL Design Engineer - SoC

CAPRUS IT PRIVATE LIMITED

5 - 9 years

0 Lacs

hyderabad telangana

Posted:1 week ago| Platform: Shine logo

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Skills Required

logic design rtl coding soc design integration verilog systemverilog lint cdc synthesis formal verification axi ahb apb scripting automation uvm pcie usb ddr design verification multi clock designs asynchronous interface asic development eco fixes amba protocols soc clocking reset architecture verification cycle functional coverage matrix comprehensive test plan regression management dut integration verification ip development system verilog assertions release process simulations regressions eth dv engineer verification engineer

Work Mode

On-site

Job Type

Full Time

Job Description

You should have experience in Logic design and RTL coding, as well as SoC design and integration for complex SoCs. Proficiency in Verilog/System-Verilog and Multi Clock designs including Asynchronous interfaces is essential. Familiarity with ASIC development tools such as Lint and CDC is required. Knowledge of Synthesis and understanding of timing concepts is a plus. Experience with ECO fixes, formal verification, and AMBA protocols like AXI, AHB, and APB, along with SoC clocking/reset architecture is necessary. Strong communication skills, proactive attitude, creativity, curiosity, motivation to learn, and good collaboration skills are expected. Your responsibilities will include understanding standards and specifications, developing architecture, documenting implementation details, hands-on work throughout the verification cycle, ensuring compliance with the latest methodologies, developing Verification IPs, defining Functional Coverage matrix and Comprehensive Test plan, managing regression and functional coverage closure, integrating and verifying DUT for IP delivery sign-off, leading a small team, and demonstrating hands-on experience in the complete verification cycle with strong verification concepts. You should have a strong knowledge of Verilog, SystemVerilog, and UVM, experience in UVM-based Verification IP development, familiarity with AMBA AXI/AHB/APB System buses, hands-on experience with PCIe/Eth/USB/DDR, expertise in System Verilog Assertions, scripting for automation, release processes, simulations, and regressions, and excellent written and oral communication skills. Leading the Verification IP development with junior engineers, exposure to the full verification cycle, and being a DV Engineer, Design Verification, or Verification Engineer are desirable skills and experiences.,

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ASIC/RTL Design Engineer - SoC