ASIC/RTL Design Engineer CAPRUS IT PRIVATE LIMITED

5.0 - 9.0 years

0 Lacs

hyderabad, all india

On-site

As a DV Engineer at our company, you will be responsible for a range of tasks related to logic design, RTL coding, SoC design, and integration for complex SoCs. Your main responsibilities will include: - Understanding the standards and specifications to ensure compliance with the latest methodologies. - Developing verification IPs and defining Functional Coverage matrix and Comprehensive Test plan. - Managing regression and functional coverage closure. - Integrating and verifying DUT for IP delivery sign-off. - Leading a small team of engineers. To excel in this role, you must possess the following qualifications: - Strong experience in Logic design and RTL coding, SoC design, and integratio...

Posted 3 weeks ago

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ASIC/RTL Design Engineer - SoC CAPRUS IT PRIVATE LIMITED

5.0 - 9.0 years

0 Lacs

hyderabad, telangana

On-site

As an experienced professional in Logic design and RTL coding, you will be required to have hands-on experience in SoC design and integration for complex SoCs. Your expertise in Verilog/System-Verilog and Multi Clock designs, including Asynchronous interface, will be crucial for this role. Additionally, your familiarity with tools in ASIC development such as Lint and CDC will be essential. Your responsibilities will include understanding standards/specifications, developing architecture, documenting implementation level details, and working on every aspect of the verification cycle. You will be responsible for compliance with the latest methodologies, developing Verification IPs, defining Fu...

Posted 1 month ago

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ASIC/RTL Design Engineer - SoC CAPRUS IT PRIVATE LIMITED

5.0 - 9.0 years

0 Lacs

hyderabad, telangana

On-site

You should have experience in Logic design and RTL coding, as well as SoC design and integration for complex SoCs. Proficiency in Verilog/System-Verilog and Multi Clock designs including Asynchronous interfaces is essential. Familiarity with ASIC development tools such as Lint and CDC is required. Knowledge of Synthesis and understanding of timing concepts is a plus. Experience with ECO fixes, formal verification, and AMBA protocols like AXI, AHB, and APB, along with SoC clocking/reset architecture is necessary. Strong communication skills, proactive attitude, creativity, curiosity, motivation to learn, and good collaboration skills are expected. Your responsibilities will include understand...

Posted 3 months ago

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