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5.0 - 9.0 years
0 Lacs
hyderabad, telangana
On-site
You should have experience in Logic design and RTL coding, as well as SoC design and integration for complex SoCs. Proficiency in Verilog/System-Verilog and Multi Clock designs including Asynchronous interfaces is essential. Familiarity with ASIC development tools such as Lint and CDC is required. Knowledge of Synthesis and understanding of timing concepts is a plus. Experience with ECO fixes, formal verification, and AMBA protocols like AXI, AHB, and APB, along with SoC clocking/reset architecture is necessary. Strong communication skills, proactive attitude, creativity, curiosity, motivation to learn, and good collaboration skills are expected. Your responsibilities will include understanding standards and specifications, developing architecture, documenting implementation details, hands-on work throughout the verification cycle, ensuring compliance with the latest methodologies, developing Verification IPs, defining Functional Coverage matrix and Comprehensive Test plan, managing regression and functional coverage closure, integrating and verifying DUT for IP delivery sign-off, leading a small team, and demonstrating hands-on experience in the complete verification cycle with strong verification concepts. You should have a strong knowledge of Verilog, SystemVerilog, and UVM, experience in UVM-based Verification IP development, familiarity with AMBA AXI/AHB/APB System buses, hands-on experience with PCIe/Eth/USB/DDR, expertise in System Verilog Assertions, scripting for automation, release processes, simulations, and regressions, and excellent written and oral communication skills. Leading the Verification IP development with junior engineers, exposure to the full verification cycle, and being a DV Engineer, Design Verification, or Verification Engineer are desirable skills and experiences.,
Posted 2 weeks ago
8.0 - 12.0 years
20 - 35 Lacs
Hyderabad
Work from Office
Job Title: SoC Infrastructure Development Lead (Dev-Lead) Experience: 8+ years Location: Hyderabad Notice Period: Immediate to 15 Days Role Overview We are looking for a highly experienced and technically strong SoC Infrastructure Development Lead to drive design, integration, and verification of infrastructure IPs that form the backbone of our complex SoC platforms. This role requires deep domain knowledge of infrastructure components such as interconnects, clocks, resets, power domains, debug fabric, and system control blocks, and the ability to coordinate across silicon, firmware, verification, and physical design teams. Key Responsibilities SoC Infrastructure Planning and Development Cross-IP Integration & SoC-Level Ownership Design Enablement & Firmware Interface Verification and Validation Required Expertise Technical Skills Strong RTL design skills using Verilog/SystemVerilog; familiarity with UVM and formal verification flows. In-depth knowledge of AMBA (AXI/AHB/APB), NoC, and coherent interconnects (e.g., CCN, CMN, or NOC from Arteris/NVIDIA). Expertise in clock tree design, clock gating strategies, and multi-domain reset and power sequencing. Experience with RTL-to-GDSII flows, including timing constraints, SDC generation, and ECO handling. Platform-Specific Expertise Experience working on Qualcomm, ARM, Intel, or custom ASIC platforms, with a solid understanding of SoC assembly and platform integration. Familiarity with: Qualcomm AOSS, RPMh, and RPM message protocol, ARM Coresight & debug/mem-ap infrastructure, Secure boot, eFuse management, and system control registers, DVFS, retention/idle states, and power collapse flows. Tools & Methodologies Proficient with tools like Synopsys Design Compiler, Primetime, VCS, SpyGlass, Questa, or Jasper. Working knowledge of scripts in Python/TCL/Perl for automation of flow and register map generation. Hands-on experience with hardware-software co-validation platforms (e.g., Synopsys ZeBu, Cadence Palladium, FPGA protos).
Posted 1 month ago
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