📍 Location: Hyderabad 💼 Experience: 10 to 20+ years 📢 Type: Full-Time | On-site About the Role: We are looking for a highly experienced and visionary Design Verification Leader to head our Full Chip Level Verification team. This is a strategic and hands-on role that will drive verification strategy, planning, execution, and team leadership across complex SoC/ASIC programs. You will work closely with architecture, design, DFT, and post-silicon validation teams to ensure first-pass silicon success, high quality, and on-time delivery. Key Responsibilities: Own and lead full-chip verification strategy, planning, and sign-off for multiple SoC/ASIC programs. Drive development and deployment of UVM-based testbenches , functional coverage, and formal verification strategies. Lead team(s) of engineers across domains, including IP, Sub-system, and SoC level verification. Collaborate with cross-functional stakeholders, including RTL design, DFT, firmware, validation, and architecture teams. Drive verification methodology standardization , automation, and reuse across programs. Deliver high-quality silicon by proactively identifying risks, debugging complex failures, and driving verification closure. Define and manage project schedules, resource allocation , and risk mitigation plans. Provide technical mentorship , performance reviews, and leadership to grow a world-class verification team. Represent the BU in technical reviews, customer discussions, and strategic planning. Required Skills and Experience: 10–20+ years of experience in ASIC/SoC design verification , with at least 5+ years in a leadership/managerial role. Strong hands-on experience with SystemVerilog, UVM, assertions (SVA), and functional coverage . Proven track record in full-chip and sub-system verification of complex SoCs or processors. Deep understanding of verification methodologies, flows, and tools (Synopsys, Cadence, Mentor). Strong debugging skills across simulation, emulation, and silicon bring-up. Experience with low-power verification (UPF), DFT-aware verification , and performance validation is a plus. Working knowledge of scripting (Python, Perl, Tcl) and regression infrastructure. Excellent project management, communication , and team leadership skills . BE/BTech or ME/MTech in Electronics, Electrical, or Computer Engineering. Preferred Qualifications: Experience working with global teams and customer engagements . Exposure to AI/ML, automotive, networking, or mobile SoC domains . Familiarity with formal verification and post-silicon validation techniques. Why Join Us? Lead cutting-edge semiconductor verification programs with global impact. Work with some of the brightest minds in VLSI and SoC development. Opportunity to drive strategy and build high-performance teams . Competitive compensation, leadership exposure, and career growth. Interested? 📧 Send your profile to hemant@sykatiya.com 📄 Let’s connect and explore how you can shape the future of silicon with us. Show more Show less
You are a highly experienced ASIC RTL Design Architect responsible for leading the design and verification of cutting-edge SoCs and high-speed digital IPs. With over 10 years of experience in ASIC/FPGA design, your expertise lies in RTL using Verilog/SystemVerilog, Lint, CDC, and Spyglass-based design verification methodologies. Your main responsibilities include leading RTL design and micro-architecture for high-performance ASIC SoCs, ensuring compliance with Lint, CDC, and SDC constraints using Spyglass or equivalent tools, driving design optimization and timing closure, as well as collaborating with cross-functional teams such as Design Verification, DFT, Physical Design, and Software teams. You will also be involved in developing and reviewing architecture specifications, coding guidelines, and best practices, as well as performing synthesis, timing analysis, and static verification using tools like STA, LEC, and Formal Verification. Key requirements for this role include a minimum of 10 years of experience in ASIC RTL design and architecture, expertise in Verilog/SystemVerilog for RTL design, strong knowledge of Spyglass Lint/CDC and static verification methodologies, experience in SoC micro-architecture, high-speed interfaces, and power optimization. Additionally, you should have a solid understanding of synthesis, STA, timing closure, backend constraints, experience with EDA tools like Synopsys, Cadence, Mentor Graphics, and familiarity with UVM-based verification and scripting languages such as TCL, Python, or Perl. Preferred qualifications include an M.Tech/MS/PhD in Electrical Engineering, Computer Engineering, or related field, experience in chip tape-out and production silicon, and an understanding of hardware security, reliability, and safety standards. If you are looking to be part of a team that is shaping the future of high-performance computing, apply now and join us in building innovative solutions together.,
Sykatiya Technology Pvt Ltd is a leading Semiconductor Industry innovator committed to leveraging cutting-edge technology to solve complex problems. We are currently looking for a highly skilled and motivated Data Scientist to join our dynamic team and contribute to our mission of driving innovation through data-driven insights. As the Lead Data Scientist and Machine Learning Engineer at Sykatiya Technology Pvt Ltd, you will play a crucial role in analyzing large datasets to uncover patterns, develop predictive models, and implement AI/ML solutions. Your responsibilities will include working on projects involving neural networks, deep learning, data mining, and natural language processing (NLP) to drive business value and enhance our products and services. Key Responsibilities: - Lead the design and implementation of machine learning models and algorithms to address complex business problems. - Utilize deep learning techniques to enhance neural network models and enhance prediction accuracy. - Conduct data mining and analysis to extract actionable insights from both structured and unstructured data. - Apply natural language processing (NLP) techniques for advanced text analytics. - Develop and maintain end-to-end data pipelines, ensuring data integrity and reliability. - Collaborate with cross-functional teams to understand business requirements and deliver data-driven solutions. - Mentor and guide junior data scientists and engineers in best practices and advanced techniques. - Stay updated with the latest advancements in AI/ML, neural networks, deep learning, data mining, and NLP. Technical Skills: - Proficiency in Python and its libraries such as NumPy, pandas, sci-kit-learn, TensorFlow, Keras, and PyTorch. - Strong understanding of machine learning algorithms and techniques. - Extensive experience with neural networks and deep learning frameworks. - Hands-on experience with data mining and analysis techniques. - Proficiency in natural language processing (NLP) tools and libraries like NLTK, spaCy, and transformers. - Proficiency in Big Data Technologies including Sqoop, Hadoop, HDFS, Hive, and PySpark. - Experience with Cloud Platforms such as AWS services like S3, Step Functions, EventBridge, Athena, RDS, Lambda, and Glue. - Strong knowledge of Database Management systems like SQL, Teradata, MySQL, PostgreSQL, and Snowflake. - Familiarity with Other Tools like ExactTarget, Marketo, SAP BO, Agile, and JIRA. - Strong Analytical Skills to analyze large datasets and derive actionable insights. - Excellent Problem-Solving Skills with the ability to think critically and creatively. - Effective Communication Skills and teamwork abilities to collaborate with various stakeholders. Experience: - At least 8 to 12 years of experience in a similar role.,
We are looking for passionate individuals who are ready to take on challenges in IP/ASIC/SOC Verification. We have open positions at all levels including Engineer, Senior Engineer, Lead, Manager, Director, and Head of Verification. The ideal candidate will have 3-20 years of experience in the field. In this role, you will be an integral part of the ASIC verification team. Your primary responsibility will be the functional verification of ASIC IPs. Our verification methodology utilizes cutting-edge techniques and tools such as coverage-driven constrained random verification and formal verification. Our design and implementation of verification environments heavily rely on object-oriented architectures and frameworks. We are seeking individuals with expertise and aptitude in verifying functions like image processing, video compression, and computer vision. As a verification engineer, you will also get the opportunity to delve into the algorithms that drive the hardware. The ideal candidate is an experienced engineer with exceptional programming skills and a genuine interest in ASIC verification. Our verification environments are complex, so a strong ability to comprehend, implement, and maintain intricate software systems is essential. Previous experience in hardware verification using SystemVerilog, UVM, low power verification, and formal methods would be advantageous. Analytical thinking, systematic approach, and attention to detail are traits we highly value in potential candidates. If you meet these criteria and are ready for an exciting challenge in the field of ASIC verification, we would love to hear from you. References are most appreciated. (ref:hirist.tech),