Verification Engineer - ASIC/UVM

We are looking for passionate individuals who are ready to take on challenges in IP/ASIC/SOC Verification. We have open positions at all levels including Engineer, Senior Engineer, Lead, Manager, Director, and Head of Verification. The ideal candidate will have 3-20 years of experience in the field. In this role, you will be an integral part of the ASIC verification team. Your primary responsibility will be the functional verification of ASIC IPs. Our verification methodology utilizes cutting-edge techniques and tools such as coverage-driven constrained random verification and formal verification. Our design and implementation of verification environments heavily rely on object-oriented architectures and frameworks. We are seeking individuals with expertise and aptitude in verifying functions like image processing, video compression, and computer vision. As a verification engineer, you will also get the opportunity to delve into the algorithms that drive the hardware. The ideal candidate is an experienced engineer with exceptional programming skills and a genuine interest in ASIC verification. Our verification environments are complex, so a strong ability to comprehend, implement, and maintain intricate software systems is essential. Previous experience in hardware verification using SystemVerilog, UVM, low power verification, and formal methods would be advantageous. Analytical thinking, systematic approach, and attention to detail are traits we highly value in potential candidates. If you meet these criteria and are ready for an exciting challenge in the field of ASIC verification, we would love to hear from you. References are most appreciated. (ref:hirist.tech),