Verification Engineer - ASIC/UVM

In this role, you will be part of the ASIC verification team responsible for functional verification of ASIC IPs. ASIC verification methodology employs state-of-the-art techniques and tools, including coverage-driven constrained random verification and formal verification. Object-oriented architectures and frameworks are a fundamental part of how we design and implement our verification environments. Expertise and aptitude towards verifying functions such as image processing, video compression, and computer vision. As a verification engineer, you will also have the opportunity to learn about the algorithms behind the hardware. **Key Responsibilities:** - Responsible for functional verification of ASIC IPs - Implement coverage-driven constrained random verification and formal verification techniques - Design and implement verification environments using object-oriented architectures and frameworks - Verify functions such as image processing, video compression, and computer vision - Learn about the algorithms behind the hardware **Qualifications Required:** - 3-20 years of experience in ASIC verification - Exceptional talent for programming - Genuine interest in ASIC verification - Prior experience in hardware verification using SystemVerilog, UVM, low power verification, and formal methods - Analytical, systematic, and attention to detail - References are most appreciated No additional details of the company were provided in the job description.,