526 Systemverilog Jobs - Page 5

Key Responsibilities: Develop and execute verification test plans based on design specifications. Create constrained-random and directed testbenches using SystemVerilog/UVM. Develop functional coverage models and drive coverage closure. Debug simulation failures, analyze waveforms, and work with RTL designers to resolve issues. Perform block-level and/or SoC-level verification. Integrate and verify 3rd-party IPs and custom IPs in subsystem and full-chip environments. Collaborate with RTL, DFT, DV, firmware, and physical design teams. Run regression simulations and ensure verification quality through coverage metrics. Automate verification flows and improve efficiency using scripting languages. Required Skills & Experience: B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or related discipline. 4–10 years of experience in digital design verification. Strong knowledge of SystemVerilog and UVM methodology. Good understanding of digital design concepts, RTL, and timing. Experience in using simulators like VCS, Incisive/Xcelium, Questa, etc. Hands-on experience with code and functional coverage, assertions, and checkers. Exposure to industry-standard protocols (AXI, AHB, I2C, SPI, PCIe, DDR, etc.). Experience in debugging RTL issues using waveform viewers (e.g., DVE, SimVision). Strong scripting skills in Python, Perl, Shell, or Make.

Role: Functional verification Engineer Skills: UVM,Verilog or SystemVerilog, SOC, ASIC, AMBA Bus Protocols Location: Hyderabad Experience: 4-10 yrs Open Positions: 8 Client: AMD Notice Period- Immediate - 45 Days Skills: asic,amba,amba bus protocols,uvm,soc,systemverilog,verilog,functional verification,dv

Job Titles: ASIC Emulation Sr. Architect We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a visionary and accomplished ASIC emulation expert with a passion for leading teams and solving complex challenges in digital design. Your career has been marked by a commitment to innovation, technical excellence, and driving results in fast-paced, collaborative environments. You have a proven track record of architecting and optimizing emulation solutions for high-performance, mixed-signal IPs, and thrive on guiding teams to deliver robust, scalable verification environments. Your leadership style fosters trust, encourages open communication, and empowers engineers to achieve their best. You are adept at bridging the gap between design and verification, and you excel at translating technical requirements into actionable plans. Your expertise extends to regression management, test coverage analysis, and the development of emulation-friendly models, ensuring projects are delivered on time and to the highest quality standards. You are customer-focused, comfortable representing your work to both internal stakeholders and external partners, and committed to continuous learning and professional development. Your ability to mentor, inspire, and innovate makes you an invaluable asset to any organization. If you are excited by the prospect of shaping the future of emulation at the forefront of semiconductor technology, you belong at Synopsys. What You’ll Be Doing: Lead the integration of verification environments and RTL into the Zebu emulation platform for seamless operation. Execute emulation tests, debug issues, and optimize environments for improved performance and reliability. Manage and analyze regression results to identify issues and ensure comprehensive test coverage. Collaborate with design and verification teams to align requirements and resolve bottlenecks effectively. Innovate and refine emulation methodologies to enhance scalability, efficiency, and reliability. Define requirements on simulation environments to enable mapping to emulation environments. Define emulation targets and test plans to be prioritized for emulation. Develop emulation-friendly Real Number Models (RNM) for mixed-signal IPs to expedite digital and firmware verification. Define emulation planning across the IP titles, report status, risks, and mitigations to emulation plan. Standardize emulation flows across PHY and controller IPs, working closely with Synopsys’ Zebu team. Represent Synopsys on customer calls regarding emulation validation strategy, plans, and progress. Lead a team of emulation engineers, providing direction, mentorship, and technical leadership. The Impact You Will Have: Drive the integration of cutting-edge verification environments into emulation platforms, ensuring high performance and reliability. Enhance the efficiency of the emulation process, leading to faster and more reliable verification of complex designs. Ensure comprehensive test coverage through meticulous regression analysis and issue identification. Collaborate effectively with design and verification teams to optimize emulation strategies and resolve bottlenecks. Innovate emulation methodologies, contributing to the scalability and efficiency of verification processes. Develop and implement emulation models that accelerate the verification of mixed-signal IPs. Standardize emulation processes across various IPs, promoting consistency and best practices. Represent Synopsys in customer interactions, showcasing expertise in emulation validation. Lead and mentor a team of emulation engineers, fostering a collaborative and innovative environment. What You’ll Need: 20+ years of hands-on emulation experience on platforms such as Palladium, Veloce, or Zebu. Extensive knowledge of design mapping, testbench mapping, and transactor development for emulation environments. Expertise in hardware/software debug solutions tailored to emulation, with excellent debugging skills in functional and gate-level simulations. Strong programming skills in object-oriented languages such as C++, Java, or Python, and scripting languages like PERL, TCL, and Shell scripts. Hands-on experience with verification metrics, including functional, code, and assertion coverage. Comprehensive knowledge of protocols, including PCIe, I2C, and Ethernet packet headers. Familiarity with multi-domain verification environments, SystemVerilog DPI, and collaborative workflows using Git, Jenkins, or CI/CD pipelines. Strong analytical and problem-solving skills, with a proven ability to mentor junior engineers and collaborate effectively. Who You Are: A strong leader with excellent communication and mentoring skills. Innovative and committed to continuous improvement. Detail-oriented with a strategic mindset. Collaborative, with the ability to work effectively in a team environment. Passionate about technology and eager to work on cutting-edge projects. The Team You’ll Be A Part Of: You will be part of a dynamic team focused on driving innovation and excellence in the emulation of state-of-the-art protocol IPs. The team collaborates closely with design and verification teams to ensure the successful integration and optimization of verification environments. As a key member of this team, you will lead and mentor a group of talented engineers, fostering a culture of collaboration and innovation. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Siemens EDA, a part of Siemens Digital Industries Software, is a global technology leader in electronic design automation. Our technologies enable companies around the world to develop new, highly innovative electronic products faster and more cost-effectively. Our customers use our solutions to push the boundaries of technology to deliver better products in the increasingly complex world of chip, board, and system design. Listener, Understander, Doer. Customers around the world trust in our products and our application engineers significantly contribute to that. You are the first on the scene to tackle any technical problem. You are a competent adviser, team player, and make things possible. “Unsolvable” is a foreign term, and you don’t do “unfair.” Your focus on the customers’ needs makes you an invaluable partner. When you join our team, you will reach one hundred percent in your career. As an integral part of the technical team, you will contribute to Siemens EDA by increasing productivity and customer satisfaction Siemens EDA’s Verification platform. This is an ambitious position that will assist in growing Siemens's business in India. Your new role: results-oriented and futuristic You will be working collaboratively with customers as well as customer support and engineering teams to optimally deploy Siemens EDA’s Questa products and services. You’ll fosters a climate conducive to help grow customer satisfaction with Siemens’ tools by helping them successfully deploy new flows and methodologies. Optionally mentor and lead a team of application engineers, supervise and guide them on the accounts and engagements that they are working on. You’ll be working with customers with varying design styles and methodologies to craft the most effective technical solutions. You’ll provide key expert advice and contribute to technical campaigns in other regions. Identify and qualify potential new business opportunities and work the account teams to build an engagement plan. Work with Account Managers and the world-wide teams for forming strategies and driving Siemens’ tools for customer projects to enable business success for Siemens EDA. Become a trusted advisor to your customers. Will have moderate travel within India and abroad We are not looking for superheroes, just super minds You’re a Graduate / Post Graduate (Bachelors/Masters) Electronics and Communication (E&C) / Electrical / Telecom Engineering / Computer Engineering with 4 - 10 years of meaningful experience in Digital design and Clock Domain Crossing or Lint EDA tools. You’ve solid understanding on VHDL/Verilog, SystemVerilog and Assertions. Well versed with Multiple Clock and Reset Domains and Asynchronous clock or reset domain crossing verification (Clock Domain Crossing - CDC & Reset Domain Crossing - RDC) on designs Expertise in CDC tools like Questa/0in CDC, Spyglass or VC- CDC, or other CDC products is expected Expertise in Formal Verification products like Questa Formal, Jasper or any other Formal products is a plus Low power verification techniques using UPF and CPF is a plus Exposure to static timing analysis (STA) flows involving SDC is a plus We’ve got quite a lot to offer. How about you? This role is based in Noida and you’ll get the chance to work with teams impacting entire cities, countries – and the shape of things to come. We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we encourage applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status.

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Systems Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Systems Engineer, you will research, design, develop, simulate, and/or validate systems-level software, hardware, architecture, algorithms, and solutions that enables the development of cutting-edge technology. Qualcomm Systems Engineers collaborate across functional teams to meet and exceed system-level requirements and standards. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 1+ year of Systems Engineering or related work experience. Job Overview Work with Qualcomm's security architecture / IP and access control team on next generation SOC for smartphone, tablet, automotive and IOT product categories. is responsible for assisting product development teams throughout the company to apply secure HW design principles to individual blocks, computing cores, and at the SoC level. SW/HW co-design, HW development experience. Familiarity with debug architectures such as JTAG and ARM coresight are a plus Successful candidates will be able to engage with product teams independently with minimal supervision to detect and mitigate security vulnerabilities in hardware architecture and implementations, involve in access control issues at both SW and HW. Minimum Qualifications 6 to 12 years of industry or academic experience in Security are required. Additionally, applicants must have expertise in two or more of the following areas: Computer architecture and hardware based or assisted access control and security Mobile platform security, Secure Boot, Secure Storage, Access Control, Secure Debug, DDR protection ARM TrustZone, Virtualization Operating system security and hypervisor security languages: C/C++, Python, RTL Teamwork across various teams and geolocations. Able to communicate in English, both verbal and written. Preferred Qualifications The following skills/experience will be considered a plus: ARM architecture SoC security design Applied Cryptography Trusted Computing Working Knowledge on hardware firewalls for access control Knowledge on AI/ML is added advantage SystemVerilog, VHDL, Verilog, SystemC - FPGA/ASIC design is a plus Side channel attacks, power analysis and timing attacks on crypto elements is a plus Memory technology (DDR4, DDR5), storage technologies is (eMMC, UFS) is a plus Educational Requirements: Required: Bachelor degree and above, Computer Engineering and/or Electrical Engineering Experience Requirements: Bachelor’s/ Masters with 5-7+ years Systems Engineering or related work experience Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3065402

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Roles and Responsibilities Qualcomm modem team is looking for world-class RTL design engineers looking to work on cutting edge wireless technology, which will be deployed worldwide in our industry leading devices. You will be contributing to RTL design and integration of one or more flagship Modem core IPs. Responsibilities include: Microarchitecture development and specification. From early high-level architectural exploration, through micro architectural research and arriving at a detailed specification. RTL ownership. Development, assessment, and refinement of RTL design to target power, performance, area, and timing goals Working collaboratively with block designers, verification, architecture, implementation, and post-silicon teams to resolve issues and ensure timely project execution. Collaborating with cross-functional teams, debugging and identifying issues, providing workarounds, and making recommendations on bug fixes. Skillset Required The candidate must have at least 1 to 4 years of front-end ASIC RTL design experience. The candidate must be strong in design micro-architecture and RTL coding (SystemVerilog / Verilog / VHDL). Other requirements include: Hands-on experience with multi-clock designs. Exposure to synthesis and STA. Awareness of low power and high-speed design. Knowledge of industry-standard front-end tool flows (lint, CDC, etc.). Strong critical thinking, problem-solving, and debugging skills. Good communication and interpersonal skills. Flexible to work with multi-geo teams. Minimum Qualifications: Bachelor’s degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field and 9-13 years of hardware engineering or related work experience. OR Master’s degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field and 8-12 years of hardware engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field and 5+ years of hardware engineering or related work experience. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3073973

Meta is hiring talented individuals to join our Infrastructure organization as ASIC Frontend Implementation Engineers (RDC/CDC). In this role, you will play a critical part in designing and developing efficient System on Chip (SoC) and IP for data center applications. As an ASIC Frontend Implementation Engineer, your primary focus will be on the front-end implementation process and static verification tools, transforming RTL designs into optimized netlists. You will utilize your expertise in RTL Lint, CDC analysis, timing constraints, and synthesis to ensure seamless integration of various components to build efficient System on Chip (SoC) and IP for data center applications.By joining our team, you'll have the opportunity to contribute to the development of cutting-edge technology that powers Meta's infrastructure. ASIC Engineer, Frontend Implementation RDC/CDC Responsibilities: Perform Flat and Hierarchical Clock Domain Crossing and work with the designers to analyze the complex clock domain crossings and sign off the CDC Perform Flat and Hierarchical Reset Domain crossing Checks. Understand the Reset-Architecture by working with Design and FW teams and develop reset groups and the corresponding reset sequence for RDC Perform RTL Lint and work with the Designers to create waivers Perform RTL DFT Analysis and improve the DFT coverage for Stuck-at faults Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power Developing Automation scripts and Methodology for all Front End (FE)-tools including (Lint, CDC, RDC,) Work closely with the Design Engineers, DV Engineers, Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback Minimum Qualifications: Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 2+ years of experience in static verification tools Experience with Lint, Clock Domain & Reset Domain crossing Knowledge of SOC Integration (Clocking, Reset, PLL, etc) Knowledge of front-end ASIC flows Experience with RTL design using SystemVerilog or other HDL Successful candidates must remain in role in the same team in India for a minimum period of 24 months before being eligible for transfer to another role, team or location Preferred Qualifications: Scripting and programming experience using Perl/Python, TCL, and Make Experience with Design Compiler, Spyglass, PrimeTime, Formality or equivalent tools Experience with SOC Design Integration and Front-End Implementation Experience with developing structural rule based checks for RTL & Netlist Experience with Netlist-CDC Analysis and improving MTBF Knowledge of Timing/physical libraries, SRAM Memories About Meta: Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics. Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.

You have an immediate opening for the position of Lead RTL Design in Hyderabad with Modern Chip Solutions. As a Lead RTL Design Engineer at Modern Chip Solutions, you will be responsible for integrating various IPs into the SoC, performing static checks, and enhancing IPs as per the SoC requirements. You should have at least 8+ years of experience, a strong understanding of SystemVerilog, scripting skills in Perl/Python, good debugging abilities, and excellent documentation skills. Key Responsibilities: - Integrating various IPs into the SoC - Performing static checks - Enhancing IPs based on SoC requirements Qualifications: - Experience: 8+ years - Location: Hyderabad - Notice Period: Immediate Required Skills: - Strong understanding of SystemVerilog - Scripting skills (Perl/Python) - Good debugging and documentation skills Preferred Skills: - Experience in SoC integration - Knowledge of CDC and Lint analysis Modern Chip Solutions is an equal opportunity employer, dedicated to fostering diversity and creating an inclusive work environment for all employees. If you are interested in this position, please send your updated profile to naveen.a@modernchipsolutions.com.,

Overview: WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Responsibilities: ASIC Verification THE ROLE : We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The Verification Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Develop/Maintain tests for functional verification and performance verification at the core level Build testbench components to support the next generation IP Maintain or improve current test libraries to support IP level testing Create hardware emulation build to verify the IP functional performance Maintain and improve current hardware emulation environment to speed up the runtime performance and improve the debug facility Provide technical support to other teams PREFERRED EXPERIENCE: 4+yrs of proficient experience in SoC and IP level RTL verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++ Developing UVM based verification frameworks and testbenches, processes and flows Knowldgeable on AMBA protocols like APB/AHB/AXI etc Required protocols knowledge like USB, I3C, UFS, QSPI etc Automating workflows in a distributed compute environment. Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Scripting language experience: Perl, Python, Makefile, shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to ARM & RISCV architecture. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-MK1 Qualifications: Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

The Infra Silicon team at Meta is responsible for designing and building in-house hardware accelerator Application-Specific Integrated Circuits (ASICs) to enhance Meta's computing efforts with capacity and efficiency at lower power and cost. The team focuses on creating domain-specific System on Chips (SoCs) that enable Meta's data centers to execute computationally-intensive workloads, such as video transcoding and AI/ML, with higher performance and lower energy consumption. They are organized into several key areas, including architecture & algorithms, design & micro-architecture, design verification, implementation & backend design, emulation/prototyping, and system on chip (SoC), which collaborate extensively with other teams to deliver comprehensive solutions for various technical domains. ASIC Engineer, Implementation Responsibilities: Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power. Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them Perform Power Estimation at RTL and Gate Level and identify power reduction opportunities Run Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic Equivalency failures Perform RTL Lint and work with the Designers to create waivers Perform RTL DFT Analysis and improve the DFT coverage for Stuck-at faults Perform Flat and Hierarchical Clock Domain Crossing and work with the designers to analyze the complex clock domain crossings and sign off the CDC Perform Flat and Hierarchical Reset Domain crossing Checks. Understand the Reset-Architecture by working with Design and FW teams and develop reset groups and the corresponding reset sequence for RDC Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top-level including SOC. Analyze the inter-block timing and come up with IO budgets for the various partition blocks Develop Power Intent Specification in UPF for the multi-Vdd designs Developing Automation scripts and Methodology for all FE-tools including (Lint, CDC, RDC, Synthesis, STA, Power) Work closely with the Design Engineers, DV Engineers, Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback Minimum Qualifications: Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 2+ years of experience in Design Integration and Front-End Implementation Experience with Register-Transfer Level (RTL) Synthesis and design optimization for Power, Performance, Area Knowledge of front-end and back-end ASIC tools. Experience with RTL design using SystemVerilog or other Hardware Description Language (HDL) Experience managing multiple design releases and working with cross functional teams to support and debug timing, area, power issues Experience with Electronic Design Automation (EDA) tools and scripting languages (Python, TCL) used to build tools and flows for complex environments. Experience with communicating across functional internal teams and vendors Preferred Qualifications: Experience Knowledge of Register-Transfer Level (RTL) coding using Verilog/System Verilog. Knowledge of Timing/physical libraries, Static Random Access Memory (SRAM) Experience with Power, Performance, Area Analysis and techniques for reducing power Knowledge of Clock Domain Crossing, Reset Domain Crossing, Logic Error Correction (LEC) Scripting and programming experience using Perl/Python, TCL, and Make Knowledge of Low power design. Experience with Design Compiler, Spyglass, PrimeTime, Formality or equivalent tools Synthesis Background, Timing Constraints Development, Floorplanning and Static Timing Analysis (STA) About Meta: Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics. Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.

As a candidate for this position, you should hold a Bachelor's degree in Computer Science, IT, a related field, or possess equivalent practical experience. Additionally, you should have at least 5 years of experience in static timing analysis, synthesis, physical design, and automation. It is crucial that you have expertise in physical design tool automation, including synthesis, P&R, and sign-off tools. In addition to the minimum qualifications, preferred qualifications for this role include experience in extracting design parameters, Quality of Results metrics, and analyzing data trends. You should also have knowledge of timing constraints, convergence, and signoff processes, as well as familiarity with parasitic extraction tools and flow. Proficiency in Register-Transfer Level (RTL) languages such as Verilog/SystemVerilog is required, along with a strong understanding of Static Timing Analysis (STA), Electromigration and IR Drop (EMIR), and PDV signoff methodologies. Join a dynamic team that is dedicated to pushing boundaries and developing custom silicon solutions that drive the future of Google's direct-to-consumer products. Your contributions will play a key role in innovating products that are beloved by millions worldwide. By leveraging your expertise, you will help shape the next generation of hardware experiences that deliver unparalleled performance, efficiency, and integration. In this role, your responsibilities will include driving sign-off timing methodologies for mobile System on a chip (SoCs) to optimize Power Performance Area (PPA) and yield. You will analyze power performance area trade-offs across various methodologies and technologies, as well as work on prototyping subsystems to deliver optimized PPA recipes. Collaboration with cross-functional teams including architecture, Internet Protocols (IPs), design, power, and sign-off methodology is essential. Furthermore, you will engage with foundry partners to enhance signoff methodology for improved convergence and yield.,

You are an experienced and highly skilled Senior SOC Design Verification Engineer with over 10 years of experience, specializing in PCIE (Peripheral Component Interconnect Express) protocols. As a key member of the team at Eximietas Design, you will be responsible for ensuring the robustness and correctness of cutting-edge System on Chip (SoC) designs. Your role will involve developing and implementing verification plans for complex SoC designs, with a particular focus on PCIE subsystems. You will work on creating and maintaining advanced testbenches using SystemVerilog and UVM (Universal Verification Methodology), as well as writing and executing test cases to verify functional and performance requirements, especially for PCIE protocols. Your responsibilities will also include debugging and resolving functional and performance issues in collaboration with design and architecture teams, developing and enhancing verification environments for PCIE and related interfaces, performing coverage-driven verification, and ensuring coverage closure. You will collaborate with cross-functional teams to define verification strategies and methodologies, mentor junior engineers, and contribute to the continuous improvement of verification processes. To qualify for this role, you should have a strong background in SoC design verification, with expertise in SystemVerilog, UVM, and PCIE specifications (e.g., PCIE Gen3/Gen4/Gen5) and verification methodologies. You should be proficient in developing and debugging complex testbenches and test cases for PCIE subsystems, with experience in coverage-driven verification and achieving coverage closure. Familiarity with AMBA protocols (AXI, AHB, APB), low-power verification techniques, power-aware simulation, and formal verification tools and methodologies will be beneficial. Strong problem-solving skills, attention to detail, excellent communication, and teamwork skills are essential for this role. Preferred skills for this position include knowledge of scripting languages like Python, Perl, or Tcl, familiarity with machine learning accelerators or AI/ML-based SoC designs, and experience with advanced process nodes (e.g., 7nm, 5nm). In return, Eximietas Design offers you the opportunity to work on cutting-edge SoC designs and innovative technologies in a collaborative and inclusive work environment. You will receive a competitive compensation and benefits package, along with professional growth and development opportunities.,

As an intern in the SOC design team at MIPS, you will have the opportunity to be part of a 6-month or 1-year program. Candidates who have graduated in 2026 or later are eligible to apply, with 2025 graduates not meeting the qualification criteria. To be considered for this internship, you should possess a Master's or Bachelor's degree in Electronics Engineering, Electronics and Telecommunication Engineering, Computer Science, or Electrical Engineering. A strong academic track record with a CGPA of 8.0 or higher is preferred. The internship positions are available in Pune and Bangalore. Your main responsibilities will include designing and integrating subsystems into SoCs and contributing to the definition of RTL development flows for MIPS RISC-V processors. The key skills required for this role include proficiency in Verilog, SystemVerilog, VCS, Verdi, as well as strong scripting abilities in languages such as Tcl, Python, and Perl. Additionally, strong debugging skills will be beneficial in carrying out your day-to-day tasks effectively.,

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. You should possess at least 5 years of experience in ASIC development with Verilog/SystemVerilog and VHDL. It is essential to have experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT). Additionally, experience in micro-architecture and design of subsystems is required. Preferred qualifications: Ideally, you should have experience in SoC designs and integration flows. Proficiency in scripting languages such as Python or Perl would be beneficial. Knowledge of high performance and low power design techniques is preferred, along with an understanding of arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies. About the job: As a member of our team, you will contribute to shaping the future of AI/ML hardware acceleration, focusing on cutting-edge TPU (Tensor Processing Unit) technology that drives Google's most demanding AI/ML applications. Your responsibilities will involve verifying complex digital designs, specifically related to TPU architecture and its integration within AI/ML-driven systems. You will work on ASICs used to enhance data center traffic, collaborating with various teams to deliver high-quality designs for next-generation data center accelerators. Innovation, problem-solving, and evaluation of design options will be key aspects of your role, with a focus on micro-architecture and logic solutions. The ML, Systems, & Cloud AI (MSCA) organization at Google is responsible for designing, implementing, and managing the hardware, software, machine learning, and systems infrastructure for all Google services and Google Cloud. Prioritizing security, efficiency, and reliability, the team works towards shaping the future of hyperscale computing, impacting users worldwide. Responsibilities: - Own microarchitecture and implementation of subsystems in the data center domain. - Collaborate with Architecture, Firmware, and Software teams to drive feature closure and develop microarchitecture specifications. - Perform Quality check flows like Lint, CDC, RDC, VCLP. - Drive design methodology, libraries, debug, and code review in coordination with other IPs Design Verification (DV) teams and physical design teams. - Identify and implement power, performance, and area improvements for the domains owned.,

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and skilled R&D Engineer with a deep understanding of system verification. You are enthusiastic about developing cutting-edge verification solutions for high-performance computing, data centers, mobile/client devices, automotive systems, and IoT segments. Your experience in architecting and building SystemVerilog UVM-based verification components, coupled with your expertise in cache coherency protocols and functional verification, makes you an ideal candidate for this role. You are a team player with excellent problem-solving abilities, strong analytical skills, and a keen attention to detail. Your background in verification IP development and your programming prowess in languages like Perl, Python, and Shell scripting set you apart as a valuable asset to our team. What You’ll Be Doing: Responsible for functional verification involving coherent and non-coherent IP designs. Collaborating with market leaders in High Performance Computing, Data Centre, Mobile/Client, Automotive, and IoT segments to define and develop products that meet complex verification requirements. Architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. Developing verification plans and driving functional coverage-driven verification closure of real designs. Debugging and resolving issues in verification environments to ensure robust and reliable verification processes. The Impact You Will Have: Enhancing the reliability and performance of high-performance computing and data center systems through rigorous verification processes. Contributing to the advancement of mobile and client devices by ensuring the integrity and functionality of their verification protocols. Driving innovation in the automotive sector by developing robust verification solutions for automotive systems. Supporting the growth of IoT applications by providing reliable and efficient verification for IoT devices. Collaborating with industry leaders to shape the future of system verification and contribute to technological advancements. Ensuring the successful implementation and integration of verification IPs, thereby enhancing the overall quality of our products. What You’ll Need: B.E/B.Tech in Electrical Engineering/Electronics & Communications Engineering with 10-15 years of relevant experience, OR M.E/M.Tech in VLSI Design/Microelectronics with 9-12 years of relevant experience. Hands-on experience in architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. You will be responsible for functional verification involving coherent and non-coherent IP designs. Protocol experience: Should have experience on UCIe/PCIe/CXL/Unipro/USB/MIPI/HDMI/Ethernet/DDR/LPDDR/HBM memory protocol Who You Are: Excellent problem-solving, debugging, and analytical skills. Strong programming skills and familiarity with object-oriented programming concepts. Creative and innovative mindset. Excellent verbal and written communication skills. A collaborative team player with a passion for functional verification.

As a SOC Verification Engineer at Mirafra Technologies in Hyderabad, you will be responsible for performing System-level RTL verification, including FWHW coverification, SoC boot-flow, and integration-level validation. Your tasks will involve developing and verifying post-silicon validation sequences using C/C++, building and enhancing methodology-driven UVM testbenches, and collaborating on comprehensive test-plan development. You are expected to demonstrate solid expertise in Verilog, SystemVerilog, and C/C++, along with a strong working knowledge of the JTAG protocol. To excel in this role, you should have a strong background in SoC/Integration-level verification, ideally with UVM methodology. Hands-on experience in creating testplans, testbenches, and driving coverage closure is essential. Your proven skills in RTL coding and post-silicon validation, coupled with excellent debugging and collaboration capabilities, will be crucial for success in this position. By joining our team, you will have the opportunity to work on complex SoC designs and cutting-edge validation flows, shaping the future of SoC verification. Mirafra Technologies offers an innovative environment in Hyderabad that values expertise and creativity, allowing you to thrive and contribute to impactful projects. If you are passionate about SOC verification, have the required skills and experience, and are looking to join a dynamic team at the forefront of technology, we encourage you to apply. Feel free to share your CV at swarnamanjari@mirafra.com or tag and recommend this opportunity to individuals who match this profile. Join us at Mirafra Technologies and be part of a team that is driving innovation in SOC verification.,

We are looking for 2 AMS (Analog Mixed Signal) verification engineers who possess more than 5 years of experience, have hands-on RNM modeling exposure, and are well-versed with Cadence AMS/DMS Flow. As an AMS Verification Engineer, you should have the following skills: - Strong RNM modeling skills. - Proficiency with Cadence AMS/DMS flow. - Experience with SystemVerilog and Verilog-AMS. - Knowledge of analog and mixed-signal design principles. - Experience with UVM (Universal Verification Methodology). - Ability to debug AMS modeling issues. - Experience with basic scripting/automation. - Good communication and documentation skills. Your responsibilities will include: - Developing and executing verification plans for AMS designs. - Creating and automating testbenches for AMS verification. - Building and maintaining SystemVerilog real number models. - Working with analog and digital design teams to ensure designs meet specifications. - Verifying AMS/DMS IP/chip functionality. If you meet the above requirements and are eager to contribute to a dynamic team, we would like to hear from you.,

Role Summary We are looking for experienced Design Verification Engineers who have built UVM- based testbenches from scratch and contributed to multiple successful tapeouts. Candidates should have deep expertise in functional verification using SystemVerilog and UVM and be comfortable owning verification deliverables end-to-end. Job Title: Senior / Lead Design Verification Engineer Experience: 6 – 10 years Location: Siruseri, Chennai (Work from Office only) Industry: Semiconductor / VLSI Employment Type: Full-time / Permanent Key Responsibilities  Perform functional verification at block and chip level for complex ASIC/SoC designs.  Build UVM-based testbenches from scratch for new IPs or subsystems.  Develop and execute detailed verification test plans based on design specifications.  Write directed and constrained-random test cases; debug simulation failures.  Perform coverage analysis (functional and code) and drive closure.  Work with RAL (Register Abstraction Layer) to verify register-level functionality.  Develop and validate assertions (SVA) for protocol and functional correctness.  Collaborate closely with RTL, DFT, and GLS teams to ensure alignment across design phases.  Participate in multiple tapeouts, ensuring verification quality and delivery. Required Skills  Strong hands-on experience with SystemVerilog and UVM methodology.  Solid knowledge of SoC/ASIC architecture and verification lifecycle.  Hands-on experience in writing testbenches, stimulus, checkers, monitors, and scoreboards .  Strong debugging skills using simulation tools like VCS, Questa.  Experience with functional and code coverage.  Familiarity with Register Abstraction Layer (RAL) modeling and verification.  Excellent analytical and problem-solving skills.  Strong communication and teamwork abilities. Candidate Requirements  Education: B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, or related fields.  Experience: 6–10 years of relevant experience in ASIC/SoC design verification.  Must have contributed to at least three or more successful tapeouts.

Job Title: VLSI Design Engineer Location: India Experience: Varies (typically 6–10+ years) Job Summary: We are seeking a talented and motivated VLSI Design Engineer to be part of our front-end design team working on advanced SoC/ASIC products. The role involves RTL design, IP integration, and working across multiple design phases for cutting-edge semiconductor solutions. Key Responsibilities: Develop RTL using Verilog/SystemVerilog for IPs and sub-systems. Participate in microarchitecture definition and design specifications. Integrate third-party and custom IPs into larger SoC designs. Perform synthesis, lint, CDC checks, and support timing closure. Work with verification and physical design teams for design convergence. Ensure power, area, and performance goals are met. Required Skills: Strong expertise in Verilog/SystemVerilog RTL design. Solid understanding of digital logic design and VLSI principles. Experience in SoC or ASIC design flow. Familiar with industry-standard bus protocols (AXI, AHB, APB). Hands-on experience with tools like Design Compiler, PrimeTime, and SpyGlass. Scripting skills in TCL, Perl, or Python are a plus.

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Job Description Collaborate with system architects and micro-architects to define high-level, implementable SoC specifications. Own end-to-end SOC RTL delivery while analysing and optimizing design for power, performance, and area (PPA) targets. Influence SoC definition, features, and adopt physical design friendly partitioning. Lead RTL design and integration of multi-subsystem SoCs, supporting complex architectures with multi-core, multi-power, and multi-reset domains. Demonstrate strong proficiency with front-end flows, including Lint, CDC, low-power (UPF) checks, synthesis, DFT, and Static Timing Analysis (STA). Drive the development of robust Safety, Security, and Debug architectures for advanced SoCs with multiple interconnects. Design and integrate standard interface protocols such as AHB, AXI, CHI, and memory interfaces including ROM, RAM, Flash, LPDDR/DDR3/4. Engage cross-functionally with DFT, physical design, verification, emulation, and validation teams to ensure first-time-right silicon and on-time project delivery. Support post-silicon debug, bring-up, and validation, working closely with lab and silicon validation teams. Continuously evaluate and adopt new design methodologies and best practices to improve productivity and shift-left the design cycle. Mentor junior engineers, review their work, and provide technical leadership and guidance across multiple design projects. Provide overall leadership and tracking of the team’s goals. Contribute to the innovation quotient of the team via Desing Patents, Industry Standard Publications, AI-enabled design methodologies etc. Qualifications M.Tech/ B.Tech in Electrical Engineering or Computer Science with 12+ years of RTL design experience. Proven expertise in Verilog/SystemVerilog RTL design, integration, and microarchitecture. Strong understanding of SoC architecture, AMBA protocols (AXI, AHB, APB), clock/power domains, and memory subsystems. Experience with EDA tools for synthesis, lint, CDC, RDC, and timing analysis. Familiarity with UPF/low-power design, formal verification techniques, and static/dynamic checks. Excellent leadership, communication, and project management skills. Experience working with global cross-functional teams. Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, You Can Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Job Description Collaborate with system architects and micro-architects to define high-level, implementable SoC specifications. Own end-to-end SOC RTL delivery while analysing and optimizing design for power, performance, and area (PPA) targets. Influence SoC definition, features, and adopt physical design friendly partitioning. Lead RTL design and integration of multi-subsystem SoCs, supporting complex architectures with multi-core, multi-power, and multi-reset domains. Demonstrate strong proficiency with front-end flows, including Lint, CDC, low-power (UPF) checks, synthesis, DFT, and Static Timing Analysis (STA). Drive the development of robust Safety, Security, and Debug architectures for advanced SoCs with multiple interconnects. Design and integrate standard interface protocols such as AHB, AXI, CHI, and memory interfaces including ROM, RAM, Flash, LPDDR/DDR3/4. Engage cross-functionally with DFT, physical design, verification, emulation, and validation teams to ensure first-time-right silicon and on-time project delivery. Support post-silicon debug, bring-up, and validation, working closely with lab and silicon validation teams. Continuously evaluate and adopt new design methodologies and best practices to improve productivity and shift-left the design cycle. Mentor junior engineers, review their work, and provide technical leadership and guidance across multiple design projects. Provide overall leadership and tracking of the team’s goals. Contribute to the innovation quotient of the team via Desing Patents, Industry Standard Publications, AI-enabled design methodologies etc. Qualifications M.Tech/ B.Tech in Electrical Engineering or Computer Science with 12+ years of RTL design experience. Proven expertise in Verilog/SystemVerilog RTL design, integration, and microarchitecture. Strong understanding of SoC architecture, AMBA protocols (AXI, AHB, APB), clock/power domains, and memory subsystems. Experience with EDA tools for synthesis, lint, CDC, RDC, and timing analysis. Familiarity with UPF/low-power design, formal verification techniques, and static/dynamic checks. Excellent leadership, communication, and project management skills. Experience working with global cross-functional teams. Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, You Can Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

You will need a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. Additionally, you should have at least 4 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog. It is also essential to have experience in the design and development of Security or Audio blocks, as well as with a scripting language like Perl or Python. Familiarity with DSI2 or MIPI C/D Phy is necessary. Ideally, you should have a Master's or PhD degree in Electrical Engineering, Computer Engineering, or Computer Science. Preferred qualifications include experience with ASIC or FPGA design verification, synthesis, timing/power analysis, and DFT. Knowledge of high-performance and low-power design techniques, assertion-based formal verification, FPGA and emulation platforms, and SOC architecture is also beneficial. As a part of the team working on custom silicon solutions for Google's direct-to-consumer products, you will play a crucial role in shaping the future of hardware experiences. Your contributions will drive innovation behind products that are beloved by millions worldwide, delivering exceptional performance, efficiency, and integration. The Platforms and Devices team at Google focuses on various computing software platforms and first-party devices and services. By researching, designing, and developing new technologies, the team aims to enhance user interaction with computing, making it faster and more seamless, and creating innovative experiences for users globally. Your responsibilities will include collaborating with architects to develop microarchitecture, performing Verilog/SystemVerilog RTL coding, functional/performance simulation debugging, and conducting Lint/CDC/FV/UPF checks. You will also participate in test planning and coverage analysis, develop RTL implementations meeting power, performance, and area goals, and be involved in synthesis, timing/power closure, pre-silicon, and post-silicon bring-up. Additionally, you will create tools/scripts to automate tasks, track progress, and collaborate with multi-disciplined, multi-site teams in Architecture, RTL design, verification, DFT, and Partner Domains.,

As a Senior Digital Design Verification Engineer at Micron Technology, you will play a crucial role in ensuring the correctness and robustness of various digital designs through thorough testing and verification processes. Your responsibilities will encompass a wide range of tasks, including understanding design specifications, developing verification plans, creating testbenches, test cases, and verification environments, as well as performing functional, regression, and performance testing. You will collaborate closely with the digital design team to debug test cases, deliver accurate designs, and identify verification holes to progress towards tape-out. In this role, you will be expected to have a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field, along with at least 10 years of experience in digital design verification. Proficiency in verification languages such as SystemVerilog, UVM, and VHDL is essential, as well as a strong understanding of digital design principles and methodologies. Experience with industry-standard verification tools and formal verification techniques, along with knowledge of scripting languages like Python, Perl, or TCL, will be beneficial for success in this position. As part of the Micron Technology team, you will have the opportunity to work on cutting-edge memory and storage solutions that drive advancements in artificial intelligence and 5G applications. The company's relentless focus on technology leadership and operational excellence ensures a rich portfolio of high-performance memory and storage products delivered through the Micron and Crucial brands. If you are looking to be part of an innovative and dynamic organization that values continuous improvement and collaboration, Micron Technology is the place for you. To explore career opportunities at Micron Technology and learn more about how our innovations are shaping the future of information technology, please visit micron.com/careers. For any assistance with the application process or to request reasonable accommodations, you can reach out to hrsupport_india@micron.com. Micron Technology is committed to upholding international labor standards and prohibits the use of child labor in compliance with all applicable laws and regulations.,

AI Centre Ethernet Switching Architect India-remote. person could be based anywhere in India - Remote work will be considered for exceptional profiles Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore AI Centre Ethernet Switching Architect Position Overview We are seeking a top-notch specialist Architect with over 20 years of experience to join our team in designing and developing Ethernet switches tailored for AI datacenter backend networks. The ideal candidate will have a strong background in digital design, ASIC/FPGA development, Ethernet/TCP/IP protocols, and experience with high-performance interconnect protocols such as InfiniBand, NVLink, Infinity Fabric, UALink, Ultra Ethernet with a focus on delivering high-performance, low-latency solutions for large-scale AI workloads. Key Responsibilities Define and develop the architecture of AI Datacentre Switch Fabric from ground up Performance Modelling and optimization of latency, throughput and power efficiency of switch fabric Decompose the architecture into sub blocks for implementation by design team Implement Ethernet protocols (IEEE 802.3, 100G/400G/800G/1600G), ECMP, and congestion control, packet spraying Apply knowledge of InfiniBand/Ultra Ethernet, NVLink/UALink, or similar protocols for feature implementation. Understanding/experience of IOS/Junos or equivalent software platform Use P4 or related languages for programmable packet processing. Working with design, software, verification team for complete product solutions Documentation of architecture and stay updated on AI networking trends. Required Qualifications Education: MS/PhD in Electrical/Electronic Engineering. Technical Skills: Proficient in Verilog/SystemVerilog for design. Knowledge of Ethernet (IEEE 802.3, 100G/400G/800G/1600G), ECMP, and congestion control. Experience with InfiniBand, NVLink, or similar protocols. Proficiency in P4 or programmable data plane languages. Knowledge of UALink, Ultra Ethernet, or RDMA/RoCE. Soft Skills: Strong problem-solving, communication, and teamwork skills. Position Overview Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

You are a skilled professional with expertise in design and validation, ready to join a dynamic and innovative team. Your background includes developing and validating FPGA-based solutions, with solid knowledge of PCIe, CXL, USB, and other protocols. You are enthusiastic about tackling daily technical challenges and possess qualities such as self-motivation, proactivity, responsiveness, persistence, and outstanding problem-solving skills. Your key responsibilities will involve developing and implementing comprehensive validation plans for various interface solutions, ensuring compliance with industry standards. You will design FPGA-based solutions to support Hardware Assisted Verification (HAV) and conduct thorough testing and validation to identify and resolve issues. Collaboration with design teams, documentation of validation processes, and clear reporting to stakeholders will be essential. Additionally, you will work closely with cross-functional teams to ensure seamless project execution and stay updated on industry trends and advancements in validation methodologies and tools. To qualify for this role, you should hold a Bachelors or Masters degree in Electronics, Electrical, or Computer Engineering (or a related field) with a minimum of 8 years of design and validation experience. Your expertise should include extensive knowledge of FPGA-based design and validation methodologies, a strong understanding of high-speed protocols like PCIe, CXL, and USB, and proficiency in programming languages such as C/C++, SystemVerilog, Verilog, Perl, Python, and TCL. Experience with emulation or prototyping platforms like ZeBu or HAPS would be advantageous. Your problem-solving skills, attention to detail, communication, and collaboration abilities are crucial for effective teamwork and project success.,