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DV Engineer

DV Engineer

TekWissen

6 - 10 years

0 Lacs

karnataka

Posted:6 days ago| Platform: Shine logo

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Skills Required

systemverilog python perl uvm methodology sociplevel verification flows amba protocols tcl

Work Mode

On-site

Job Type

Full Time

Job Description

You are an Experienced Design Verification Engineer with a minimum of 6 years in pre-silicon verification. You have strong hands-on experience with SystemVerilog, UVM methodology, and a solid understanding of SoC/IP-level verification flows. Your role involves working closely with design, architecture, and post-silicon teams to ensure high-quality and robust product delivery. Your key responsibilities include developing testbenches, testcases, and verification components using SystemVerilog and UVM, creating and executing detailed verification plans based on design and architecture specifications, driving constrained-random verification, coverage closure, and debug failures, collaborating with RTL, DFT, and Firmware teams to debug issues and ensure seamless integration, building reusable, scalable, and modular verification environments, analyzing code coverage, functional coverage, and providing meaningful feedback for design improvements, performing assertion-based verification, and supporting formal verification where required. You will also participate in code reviews, test plan reviews, and contribute to process improvements. You should have a B.E./B.Tech or M.E./M.Tech in Electronics with 6+ years of experience in ASIC/IP/SoC verification. It is essential to have good knowledge of the verification flows, experience developing testbenches for block level or IP level or SOC Level verification, working in complex test-bench/model in Verilog, System Verilog, or SystemC, developing and maintaining block level test benches, proficiency in SystemVerilog, UVM, and testbench architecture, strong knowledge of AMBA protocols (AXI, AHB, APB), hands-on experience with simulation tools (VCS, Questa, XSIM, etc.), familiarity with debug tools (Verdi, DVE) and waveform analysis, solid understanding of functional coverage, assertions, and scoreboarding, and experience in writing automation scripts using Python/Perl/TCL. TekWissen Group is an equal opportunity employer supporting workforce diversity.,

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DV Engineer