Principal Engineer, ASIC Development Engineering

You will be responsible for the following: - Holding a Bachelors or Masters degree in Electronics/Electrical Engineering - Possessing a minimum of 7+ years of experience in ASIC/IP Digital Design for large SOCs - Demonstrating expertise in implementing RTL in Verilog/SV for complex designs with multiple clock domains - Having expertise with various bus matrices on AHB, AXI, and NOC designs - Demonstrating experience in ARM processor and/or NAND Flash subsystems (preferred) - Experience in low power design methodology and clock domain crossing designs - Proficiency in Spyglass Lint/CDC checks, report analysis, and signoff - Experience in Synthesis using DC, timing analysis, and closure (preferred) - Expertise in Perl, Python, TCL language is advantageous - Ability to quickly ramp-up and collaborate effectively with Verification/Validation teams - Must possess a positive attitude and a solution-oriented approach - Excellent written and verbal communication skills Qualifications: - Bachelors degree with 7+ years experience, Masters degree with 6+ years experience, or PhD with 3+ years experience in CS, CE, EE, EC, or equivalent required.,