Principal Product Validation Engineer

You should be an Electrical, Electronics, or Computer Science Engineer with a very good understanding of Hardware Description Languages (HDLs) such as Verilog and/or VHDL. It is essential to have prior experience in simulation/emulation using these languages. A good working knowledge of Electronic Design Automation (EDA) tools, with a focus on debugging design and verification issues using these tools, is required. Experience in process automation through scripting is also expected. Additionally, familiarity with SystemVerilog, C++, and Universal Verification Methodology (UVM) is highly preferred. Experience in Functional Verification of complex digital systems, such as System on Chip (SoC) Verification, utilizing a Hardware Verification Language (HVL) like SystemVerilog, is crucial. Proficiency in designing and implementing intricate functional verification environments is essential for this role. Moreover, knowledge of protocols like PCIe, USB3/4, and DisplayPort would be advantageous. Join us at Cadence, where we hire and nurture leaders and innovators who are eager to contribute to the ever-evolving world of technology. Let's work together to tackle challenges that others find insurmountable.,