DDR PHY IP DV Engineer

Advanced Micro Devices (AMD)

2 - 7 years

2 - 7 Lacs

bengaluru karnataka india

Posted:1 week ago| Platform: Foundit logo

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Skills Required

ams rtl coverage uvm systemverilog

Work Mode

On-site

Job Type

Full Time

Job Description

The ideal candidate will get to work on Verification of complex Analog Mixed Signal IPs (with significant Digital and Analog content) that are delivered to various AMD SoCs.

KEY RESPONSIBILITIES:

Verification of IP features : Feature Test plan creation, Verification of the IP in RTL, Gatesim and Analog Mixed Signal simulations.
Create methodology-based (UVM) verification testbenches and components from scratch for various IP features.
Quality deliverables through regressions
Verification coverage: code-coverage, functional coverage, assertions, to achieve 100% verification completeness
Reviews, and feedback to design/architecture teams.

PREFERRED EXPERIENCE:

Expertise in System Verilog, methodology based testbench architectures such as UVM, and System Verilog assertions
Expertise in code and functional coverage,
Excellent Problem solving and debugging skills.
Excellent Communication skills
Strong digital design knowledge, SoC design flow
Knowledge on AMS designs (SERDES or Memory PHYs such as DDR, GDDR) and Mixed signal verification methodology is an added advantage.
UPF based RTL low power verification
Prior experience in working on IPs with mixed signal content will be helpful.
Prior experience of technical leadership will be an asset.

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