About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Digital IC Design Senior Staff/Principal Engineer with Marvell, you'll be a member of the Central Engineering business group. If you picture Marvell as a wheel, Central Engineering is the center hub providing IP to be used by all the other spokes on that wheel, including Automotive, Storage, Security, and Networking. You'll be playing a crucial role in establishing ESD requirements and validating ESD solutions for Foundational IP, SerDes IP, and SOCs during the ESD qualification process. You will work closely with the Physical Design, Electrical Engineering, and SOC (System on Chip) teams to provide support from the initial design phase through failure analysis, issue root cause determination, and the development of corrective actions. Being part of interface design team, you will have opportunities for the development of IO circuit to customer specifications including the generation and delivery of final EDA views for the IP. Typical circuits to be developed include biasing blocks, over-voltage/over-current protection circuits, regulators, amplifiers, switches, and a range of closed loop feedback circuits. This team hires some of the biggest problem solvers in Silicon and has a huge impact on the work done at Marvell. The customers served by this team are often other chip companies and big tech companies, familiar names to all candidates. What You Can Expect Provide co-design support with both ESD simulations of circuits to maximize both performance and ESD protection robustness. Perform ESD design reviews and provide the required technical guidance for analog, foundational IP, SOCs, and qualification test chips for multiple technology nodes ranging from 45nm to 2nm across major foundry platforms. Validate and characterize ESD circuits using ICV PERC, Calibre PERC, TLP-based SPICE simulation, and any other industry methods and tools. Design enablement of ESD protection schemes for analog design like SerDes. This will include understanding ESD protection design, latch-up, transient latch-up as well as ESD design verification and EDA tools. Continue the development of best practices for ESD in the technologies being supported. Development and support of EDA tools for ESD design checking. Development of circuits like Driver, Receiver, Overvoltage protection circuits, Fail safe I/O, Bandgap and Voltage Regulators. What We're Looking For Bachelor's or Master's degree and/or PhD in Electrical/Electronic Engineering, Microelectronics or related fields and 8-15 years of related professional experience. Expertise in custom circuit design, handling layout effect in advanced FinFET process design rules, process variability and circuit reliability issues that affect power, speed, area, and yield. Advanced knowledge of on-chip ESD protection circuit design Advanced knowledge of CAD design tools such as Cadence and SPICE Applicant should have sufficient design experience to be able to effectively review designs and communicate ESD design deficiencies to product design engineering. Advanced knowledge of ESD relevant device physics such as snapback and other high-level injection phenomenon/device operations Fully familiar with industry ESD test standards and latest developments. Experience with verifying ESD analysis for IP and SoC level using industry standard tools and methodologies. Exposure and experience with the Custom ESD PERC code development will have added advantage to this role. Experience with simulation skills using cadence including PEX, Monte Carlo, and Corner analysis. Derive design specifications from customer requirement. Requires effective communication between multiple sites and ability to work with multiple groups. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We're dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it's like to work at Marvell, visit our page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-CP1
About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Built on decades of expertise and execution, Marvell's custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide array of flexible business models. In this unique role, you'll have the opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance processor chips in a leading-edge CMOS process technology, targeted at server, 5G/6G, automotive, and networking applications. What You Can Expect You will work with a global team on both the physical design of complex chips as well as the methodology to enable an efficient and robust design process. You will be responsible for maintaining, enhancing, and supporting Marvell's Place and Route Flow, leveraging industry-standard EDA tools. Your tasks will include performing synthesis, place and route, as well as timing analysis and closure on multiple intermediate and complex logic blocks. You will play a crucial role in developing and implementing timing and logic ECOs, collaborating closely with the RTL design team to drive modifications that address congestion and timing issues. Additionally, your involvement with the global timing team will include debugging and resolving any block-level timing issues encountered at the partition level. This position provides an exciting platform to engage with diverse engineering challenges within a collaborative and innovative environment at Marvell. What We're Looking For Have completed a Bachelor's Degree in Electrical/Computer Engineering or related fields and have 8+ years of related professional experience OR a Master's degree and/or PhD in Electrical/Computer Engineering, or related fields. In your coursework, you must have completed a digital logic course and projects that involved circuit design, testing, and timing analysis. Good understanding of standard RTL to GDS flows and methodology Good scripting skills in languages such as Perl, tcl, and Python Good object-oriented programming skills Good understanding of digital logic and computer architecture Knowledge of Verilog/VHDL Good communication skills and self-discipline contributing in a team environment. #LI-MN1 Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We're dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it's like to work at Marvell, visit our page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-MN1
About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a key CAD member of Marvell Central Engineering, you will play a leading role on developing next-generation automated design flow and its add-on tools. You will have the opportunity to use your extensive design and CAD knowledge to participate in defining the whole organization's design infrastructure, methodology and workflows. What You Can Expect . Design, implement, and maintain large-scale HPC clusters for EDA workloads, ensuring high availability, fault tolerance, and efficient resource utilization. Manage, configure, and optimize LSF job scheduling systems to support diverse verification workflows. Develop, automate, and monitor deployment, configuration, and operational processes for EDA infrastructure. Collaborate with EDA engineers and designers to refine verification flows to run optimally on the grid. Implement and advance CI/CD pipelines to streamline the deployment, testing, and monitoring of infrastructure and EDA flows. Provide troubleshooting and support for users and the infrastructure. Monitor infrastructure health, performance, and usage proactively identify, resolve, and document issues. Ensure compliance with security best practices,license management, and data protection requirements. Contribute to architectural innovation and process improvement for future scalability and efficiency. Participate in incident management teams for prompt issue resolution. What We're Looking For Bachelor's or Master's degree in Computer Science, Electrical Engineering, or related field. Proficiency with Programming or scripting in languages such as Python, Bash, or Perl for automation and workflow development. Working knowledge of Linux system administration and cluster troubleshooting. Familiarity with infrastructure-as-code, configuration management, and monitoring , DevOps SRE concepts CI/CD and GitOps. Strong communication and collaboration skills ability to work in cross-functional teams. Track record of identifying and implementing infrastructure optimizations for efficiency, throughput, and reliability. Preferred Qualifications: Experience with cloud-based EDA infrastructure or hybrid HPC environments. Familiarity with regression management tools, and workflow automation specific to silicon verification. Experience with HPC cluster management, especially using LSF/Platform LSF, in a chip verification or EDA context. Key Attributes: Analytical, detail-oriented, and proactive in identifying and solving technical problems. Passion for continuous learning and embracing new technologies and methods. Strong organizational abilities and commitment to documentation and process improvement. This role is essential in ensuring that our chip verification teams have a robust, high-performance, and adaptable infrastructure to accelerate silicon innovation. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We're dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it's like to work at Marvell, visit our page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-AB3
About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Marvell Data Centre Engineering (DCE) - Compute & Storage (CCS) BU has been at the forefront of developing and delivering leading-edge, high-performance data processing silicon platforms. By delivering a stream of technical innovations through a diverse set of fast?growing product lines, Marvell technology is powering the next?generation data processing and workload acceleration platforms for the Carrier, Cloud/Enterprise and Automotive Compute market segments. The team focusses on the Custom ASIC business, Cloud AI solutions & Enterprise/Career solutions including the CXL product line. What You Can Expect Develop and maintain testbenches for IP, subsystem, and SoC-level verification Design and implement UVM-based verification environments Write and execute directed and random test cases Perform functional coverage analysis and debug failures Collaborate with design, architecture, and validation teams to ensure verification completeness Participate in code reviews, quality improvement, and problem-solving initiatives What We're Looking For - Bachelor's degree in CS/EE with 8-12 years of relevant experience, or Master's degree in CS/EE with 8-10 years of relevant experience - Strong background in IP, Subsystem and SoC verification, including methodology and testbench development - Proficient in hardware verification languages such as Verilog, SystemVerilog, UVM, and C/C++ - Solid understanding of verification methodologies: object-oriented programming, white-box/black-box testing, directed/random testing, coverage analysis, and gate-level simulations - Experience in Unix/Linux environments scripting skills in Shell, Perl, or Python are a plus - Strong analytical and problem-solving skills - Ability to manage multiple tasks in a fast-paced environment - Excellent communication, interpersonal, and teamwork skills - Capable of interfacing effectively at all levels within and outside the organization - Proactive in participating in problem-solving and quality improvement initiatives Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We're dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it's like to work at Marvell, visit our page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-CP1
About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Marvell Data Centre Engineering (DCE) - Compute & Storage (CCS) BU has been at the forefront of developing and delivering leading-edge, high-performance data processing silicon platforms. By delivering a stream of technical innovations through a diverse set of fast?growing product lines, Marvell technology is powering the next?generation data processing and workload acceleration platforms for the Carrier, Cloud/Enterprise and Automotive Compute market segments. The team focusses on the Custom ASIC business, Cloud AI solutions & Enterprise/Career solutions including the CXL product line. What You Can Expect - SOC & Sub system verification activities - should have participated in successful completion of SOC/Subsys projects across all phases from SOC/Subsys Specification to Silicon. - Responsible for complete SOC/Subsys verification activities like - develop verification architecture and verification plan, develop UVM based testbench, Integrate in-house verification components + complex VIP's ( ARM, Cadence, Synopsys, etc), develop test cases (UVM & assembly), verify and do coverage analysis in RTL and gate level design. - Conduct reviews in all the SOC/Subsys verification phases, to achieve desired quality + on-schedule deliverables and drive SOC/Subsys verification process improvement. - Mentor junior engineers and technically guide and monitor them on their day to day technical tasks. - Work effectively with a global team and be self-motivated to manage deliverables - Communicate clearly both verbally and in writing. What We're Looking For Bachelor's degree in CS/EE with 14-18 years of relevant experience, or Master's degree in CS/EE with 12-16 years of relevant experience - Experience in SOC/Subsys level (rather than block level) verification of ARM-based SOCs experince in ARM based boot environment preferred. - Knowledgeable of ARM architecture and AMBA bus standards like AXI-4, CHI and ACE. - Experience with industry standard interfaces such as DDR, eMMC, PCIE, Ethernet and USB. - Experience in coding UVM SOC/Subsys level testbenches, BFM, scoreboards, monitors, etc. - Proficient in writing and debugging tests in UVM as well as C. - Exposure to Cadence, Synopsys, Mentor and/or ARM verification tools. - Experience with assertion-based formal verification tools. - Proficient in programming in scripting languages such as tcl and Perl. - Understanding of hardware emulation support. - Familiarity with TLMs in SystemC. - Experience in Version tools like CVS, SVN, GIT etc. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We're dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it's like to work at Marvell, visit our page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-CP1
About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Digital IC Design Staff Engineer with Marvell, you'll be a member of the DCE business group. This group focuses on custom, compute and storage solutions of Marvell. With the increased focus on the security of the products you will be involved in helping steer the SDL vision into on-going and future SoC's being worked on in the group. This team hires some of the biggest problem solvers in Silicon and has a huge impact on the work done at Marvell. The customers served by this team are often other chip companies and big tech companies, familiar names to all candidates. What You Can Expect As a Senior Staff Engineer, candidate will be responsible for developing verification plans and architecting test benches to validate DUT (Devise Under Test) functionality in simulation of application specific integrated circuit (ASIC/Integrated Circuit). Interpreting architectural and design requirements Writing verification test plans and requirements Developing and using complex test benches Implementing directed and constrained random test cases Collecting, analyzing, and enhancing functional and code coverage Debugging issues in the requirements, tools, simulation environment, test cases, and DUT Performing Object Oriented programming (System Verilog and C++) Participating in System Verilog Verification using a framework such as UVM or other industry standard methodologies Verification automation and scripting using Perl/Shell/Python . What We're Looking For BS or MS (Electrical or Computer Engineering ) or Equivalent Degree with 10+ years of experience. Proficient with System Verilog, HDL languages,UVM , Object Oriented Programming and Scripting Languages. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We're dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it's like to work at Marvell, visit our page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-CP1
About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Marvell is a leading provider of innovative technologies, including ultra-fast read channels, high-performance processors, leading edge transceivers, highly efficient analog designs, and powerful cryptographic engines. These solutions address all segments of the hard disk drive (HDD) and solid-state drive (SSD) electronics markets, providing complete solutions including controllers, product firmware, and reference board designs. Many of the same technologies have been utilized in Marvell system solutions products, powering PCs, servers, cloud, and enterprise systems. What You Can Expect As a member of our team, you will work closely with architects and technologists to influence R&D in accelerated compute, networking, storage, and security technologies, including emerging low-latency transport protocols. Intelligently structure new feature designs and other software changes so that code is scalable, maintainable, and easily mergeable to legacy products as well as new products. Develop next-generation switching and DPU-based solutions tailored for enterprise and cloud-scale environments. Implement and optimize control plane and data plane functionalities for switch platforms and DPUs. Enhance Layer 2/3 networking capabilities including VLANs, VXLAN, L2GRE, MPLS, BGP, OSPF, and multicast for scalable, resilient infrastructure. Design and optimize high-performance switching fabrics with advanced packet processing, QoS, congestion control, and telemetry. Contribute to open-source initiatives (e.g., SONiC, SAI, OVS, DPDK, ODP, Linux kernel) and help define future networking standards. Collaborate with hardware teams to bring up new Switch SoC platforms and ensure seamless hardware-software integration. Participate in code reviews, design discussions, and continuous integration processes. What We're Looking For Bachelor's/Master's degree in Computer Science, Electrical Engineering, or a related field with 4-14 years of relevant experience. Proficiency in C, C++, Python, and Lua scripting. Deep understanding of Ethernet switching, Layer 2/3 protocols, DPUs, and networking standards. Understanding of RoCE, RDMA, and DPU concepts. Strong hands-on experience with SONiC, SAI, Cumulus Linux, OVS, DPDK, ODP, and DPU technologies. Familiarity with ARM multicore SoC architecture and high-speed packet I/O. Solid grasp of networking constructs such as ACLs, LPM, EM, routing, MAC learning, QoS, bridging, and load balancing. Exposure to cloud networking, SDN, or network virtualization technologies. Strong analytical and problem-solving abilities. Excellent communication and collaboration skills, especially in distributed team environments. Proven ability to independently plan, execute, and deliver complex technical projects. A passion for continuous learning and thriving in fast-paced, innovation-driven settings. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We're dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it's like to work at Marvell, visit our page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-RS1
About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Marvell Central Engineering (CE) develops Marvell most advanced High-Speed SerDes (HSS) IPs covering multiple applications, Switch, Automotive, Storage, Optics, etc. Acting as the engine to the company, Central Engineering provides the source of power to every business unit in Marvell system. Central Engineering AMS(CE AMS) is responsible of developing Marvell SerDes IPs and supporting all Marvell business units for fast and smooth SoC production. What You Can Expect IP verification activities - should have participated in successful completion of projects across all phases from Specification to Silicon Develop and execute verification plans using random techniques and coverage analysis. Create and maintain testbenches and test cases. Perform functional and performance verification. Debug and resolve design and verification issues. Collaborate with design and architecture teams to ensure verification coverage. Mentor junior engineers and lead verification projects. What We're Looking For Strong digital logic understanding and fundamentals of digital design. Excellent skills in complex IP verification using SV/UVM with proficiency in debug techniques Experience with simulation tools (e.g., VCS) and knowledge of scripting languages (Python, Perl, TCL). Familiar with verification test planning and coverage driven verification closure, Verification strategies for directed and randomized testing and assertions Hands on verification experience on SERDES/DDR/Ethernet/PCIe/CXL protocols Strong knowledge / experience in building the verification environment from specification and should have spec to hardware bring-up experience. Experience in leading projects to determine methods and procedures on new assignments and coordinate activities of other team members to ensure successful project completion. Strong analytical and problem-solving and analytical skills . Ability to manage multiple tasks in a fast-paced environment . Excellent communication, interpersonal, and teamwork skills . Capable of interfacing effectively at all levels within and outside the organization . Proactive in participating in problem-solving and quality improvement initiatives. Bachelor's degree in Computer Science, Electrical Engineering or related fields and 8-12 years of related professional experience Master's degree in Electrical Engineering with 8-10 years experience Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We're dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it's like to work at Marvell, visit our page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-CP1
About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Marvell is a global leader in high-performance silicon and AI infrastructure, powering the world's most advanced datacenters, cloud platforms, 5G networks, and AI/ML workloads. Our innovations drive next-generation computing, networking, and storage, enabling breakthrough performance, scalability, and efficiency for the most demanding applications. This team at Marvell develops Murals, a next-generation AI/ML infrastructure simulation and design platform that enables in-depth analysis and optimization of large-scale training and inference workloads. Leveraging trace-driven simulation, performance modeling, and hardware/software co-design, the team helps shape scalable and resilient solutions for advanced workloads such as LLMs, DLRMs, GenAI, and GNNs. Working closely with system architects, hardware designers, and ML practitioners, the team explores innovative ways to optimize compute, memory, and networking subsystems across complex datacenter environments. What You Can Expect Simulation & Modeling - Implement workflows to study AI/ML workloads using trace-driven and analytical models. Performance Analysis - Profile and analyze system bottlenecks across compute, memory, and network layers. Networking Studies - Evaluate collective communication performance (all-reduce, all-to-all, reduce-scatter) across different topologies and fabrics. Tooling & Automation - Develop utilities for trace generation, merging, conversion, and visualization. Prototype & Validation - Test distributed training and inference pipelines in simulated and real environments. Hardware/Software Co-Design - Collaborate on emerging technologies (CXL, DPUs, NVLink, PCIe, UET/UEC, in-network compute). Scaling Studies - Conduct performance projections and trade-off studies for next-gen AI infrastructure. Knowledge Sharing - Document workflows, publish internal reports, and drive peer learning. What We're Looking For Bachelor's, Master's, or PhD in Computer Science, Electrical Engineering, or related field with 4-12 years of relevant professional experience. Strong foundation in computer architecture, distributed systems, AI/ML, and operating systems. Solid networking fundamentals including TCP/IP, RDMA, RoCE, UET/UEC, and switching/routing. Experience with simulation frameworks (e.g., Astra-Sim, Chakra, gem5, SST, NS-3). Hands-on with PyTorch/TensorFlow and distributed training frameworks (DDP, Horovod, DeepSpeed). Strong programming skills in Python, C++, and scripting for automation. Familiarity with interconnect and memory technologies (CXL, PCIe, NVLink, UAL). Experience with profiling, telemetry, observability, and debugging tools. Knowledge of collective communication algorithms and topology-aware scheduling. Exposure to AI accelerators, memory disaggregation, DPUs, and custom silicon. Familiarity with visualization tools (Perfetto, Chrome Tracing, Chakra Timeline, Flamegraphs). Experience with large-scale AI training pipelines and scaling studies. Interest in energy/performance trade-offs and resilience techniques. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We're dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it's like to work at Marvell, visit our page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-MN1
About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As an Analog IC Design Senior Staff Engineer with Marvell, you'll be a member of the Central Engineering business group. If you picture Marvell as a wheel, Central Engineering is the center hub providing IP to be used by all the other spokes on that wheel, including Automotive, Storage, Security, and Networking. You'll be part of a small analog team making a big impact on this organization. Additionally, Marvell has the perfect size and scale for you to learn several aspects of engineering that will be new to you, but also have the time and freedom to dive deep into the details of your specialization on most projects. What You Can Expect The candidate will be working on high-speed and high performance Analog SerDes development in advanced technology nodes, 3nm, 2nm and beyond. Participate in SerDes Architecture Development with DSP, Analog and Digital design teams. Interact closely with layout engineers to achieve required circuit performance. Working with the AE for the IP characterization and validation plan. Supporting IP Lab characterization and debugging. What We're Looking For Bachelor's degree in electrical engineering or related fields and 8+ years of related professional experience. Master's degree and/or PhD in Electrical Engineering or related fields with 6+ years of experience. In depth understanding of transistor level CMOS analog circuit design and basic building blocks (BGR, Current mirrors, op-amps, feedback circuits etc ) Experience in implementing Serial link building blocks for Tx / Rx (Driver, CTLE, FFE etc ) and clock path circuits (DLL s, phase rotators etc) Know-how of resonant clocking and inductor-based circuits is a plus. Experience in optimizing FinFET CMOS layout to minimize parasitic Knowledge in Verilog-A for analog behavioral modeling / simulation data capture Strong written, Oral communication with a drive to continuously learn and grow. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We're dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it's like to work at Marvell, visit our page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-RV1