Design Verification Engineer

0 years

0 Lacs

Posted:1 day ago| Platform: Linkedin logo

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Work Mode

On-site

Job Type

Full Time

Job Description

Responsibilities

Understand the standards/specificationsArchitecture development and documenting implementation level detailsHands on work for every aspect of verification cycleResponsible for the compliance with the latest Methodologies.Developing Verification IPsDefine Functional Coverage matrix and Comprehensive Test planRegression management and functional coverage closureDUT integration and verification for IP delivery sign-offLeading small teamPerson Specification

Required Skills

Hands-on experience of complete verification cycle with strong verification conceptsStrong knowledge of Verilog, SystemVerilog and UVMExperience in UVM based Verification IP developmentExperience in AMBA AXI/AHB/APB System busesHands on work experience on any of PCIe/Eth/USB/DDR etc.Hands on experience with System Verilog AssertionsScripting for automation, release process, simulations, regressionsGood command over written and oral communicationDesirable Skills
  • Lead the Verification IP development with 2 or more junior engineers
  • Exposure to full verification cycle

Desired Skills And Experience

DV Engineer, Design Verification, Verification Engineer

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