Design Verification Engineer

Design Verification Engineer

Experience:

Location:

• Master's degree in Electrical Engineering, Computer Engineering, or a related field (highly preferred)
• Minimum of 10+ years of experience in Design Verification for complex ASICs and SoCs
• Proven track record of successfully leading and executing verification projects
• In-depth knowledge of digital design principles, advanced verification methodologies (UVM, Formal Verification), and best practices
• Expertise in Verilog and VHDL with a strong grasp of coding styles and optimization techniques
• Extensive experience with a broad range of verification tools (simulators, formal verification tools, scripting languages)
• Excellent leadership, communication, collaboration, and problem-solving skills
• Ability to manage multiple projects, prioritize tasks, and meet aggressive deadlines