Job
Description
Company Description MosChip® Technologies is a publicly traded company specializing in Silicon and Product Engineering solutions, with over 1300 engineers located in Silicon Valley, USA, and India. Our expertise includes end-to-end silicon design, verification, systems, software, and device engineering, along with AI/ML solutions and test automation. MosChip® has an impressive track record with first-time right silicon of over 200 SoC tape-outs and has shipped millions of connectivity ICs. We provide comprehensive services including Digital IPs, Verification IPs, Mixed Signal IPs development, and Turnkey ASIC services. Role Description This is a full-time on-site role for a Senior Lead Physical Design Engineer located in Hyderabad. The Senior Lead Physical Design Engineer will be responsible for the complete physical design flow including, but not limited to, floorplanning, power planning, place and route, clock tree synthesis, and physical verification. The individual will also collaborate with cross-functional teams to ensure design specifications are met, timing closure is achieved, and design targets are aligned with company standards and customer expectations. Qualifications He/She should be able to do block level PNR including PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. Minimum of 7-15 years of experience in physical design. He/She should have worked on 7nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias. Provide technical guidance, mentoring to physical design engineers. Lead a team of Physical design engineers and be responsible for their blocks’ closure Interface with front-end ASIC teams to resolve issues. Low Power Design - Voltage Islands, Power Gating, Substrate-bias techniques. Expertise in Timing closure on high speed interfaces is a plus Excellent communication skills. Strong Back ground of ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure. Extensive experience and detailed knowledge in Cadence or Synopsys. Expertise in scripting languages such as PERL, TCL. Strong Physical Verification skill set. Static Timing Analysis in Primetime or Primetime-SI. Good written and oral communication skills. Ability to clearly document plans. Ability to interface with different teams and prioritize work based on project needs. Show more Show less
