Design Engineering Architech

3 - 7 years

0 Lacs

Posted:2 days ago| Platform: Shine logo

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Work Mode

On-site

Job Type

Full Time

Job Description

As a member of the team at Cadence, your role will involve: - Designing and implementing DFT IP with Verilog/SystemVerilog and/or VHDL - Designing and implementing RTL for DFT IP including POST, IST - Developing synthesis automation for DFT IP, which includes synthesis and timing constraints, RTL insertion, and verification - Owning and maintaining, extending, and enhancing existing DFT IP like LBIST At Cadence, you will be part of a team that is focused on doing work that matters and solving challenges that others may find difficult. Join us in making an impact on the world of technology.,

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Cadence

Software, Electronic Design Automation

San Jose

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