3.0 - 7.0 years

0 Lacs

noida, uttar pradesh

On-site

You will be responsible for: - Designing and implementing DFT IP with Verilog/SystemVerilog and/or VHDL - Designing and implementing RTL for DFT IP including POST, IST - Developing synthesis automation for DFT IP including synthesis and timing constraints, RTL insertion, and verification - Owning and maintaining, extending, and enhancing existing DFT IP like LBIST At Cadence, you will have the opportunity to work on impactful projects in the world of technology. Join us in solving challenges that others can't.,

Posted 1 week ago

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Design Engineering Architech Cadence Design Systems

3.0 - 7.0 years

0 Lacs

karnataka

On-site

As a member of the team at Cadence, you will play a key role in designing and implementing DFT IP using Verilog/SystemVerilog and/or VHDL. Your responsibilities will include: - Designing and implementing RTL for DFT IP including POST and IST - Developing synthesis automation for DFT IP, which encompasses synthesis and timing constraints, RTL insertion, and verification - Taking ownership of existing DFT IP like LBIST, maintaining, extending, and enhancing it Cadence is dedicated to tackling meaningful challenges in the world of technology, and as part of our team, you will have the opportunity to contribute to work that truly makes a difference.,

Posted 3 weeks ago

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Design Engineering Architect Cadence Design Systems

3.0 - 7.0 years

0 Lacs

karnataka

On-site

As a member of the team at Cadence, you will be responsible for designing and implementing DFT IP using Verilog/SystemVerilog and/or VHDL. Your role will involve creating RTL for DFT IP, including POST and IST. Additionally, you will be developing synthesis automation for DFT IP, which includes synthesis and timing constraints, RTL insertion, and verification. You will also have the opportunity to own, maintain, extend, and enhance existing DFT IP like LBIST. Qualifications required for this role: - Proficiency in Verilog/SystemVerilog and/or VHDL - Experience in designing and implementing DFT IP - Knowledge of synthesis automation for DFT IP - Familiarity with POST, IST, LBIST, synthesis, a...

Posted 3 weeks ago

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Design Engineering Architech Cadence

3.0 - 7.0 years

0 Lacs

karnataka

On-site

As a member of the team at Cadence, your role will involve: - Designing and implementing DFT IP with Verilog/SystemVerilog and/or VHDL - Designing and implementing RTL for DFT IP including POST, IST - Developing synthesis automation for DFT IP, which includes synthesis and timing constraints, RTL insertion, and verification - Owning and maintaining, extending, and enhancing existing DFT IP like LBIST At Cadence, you will be part of a team that is focused on doing work that matters and solving challenges that others may find difficult. Join us in making an impact on the world of technology.,

Posted 3 months ago

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Design Engineering Architech Cadence Design Systems

3.0 - 7.0 years

0 Lacs

karnataka

On-site

You will be responsible for designing and implementing DFT IP using Verilog/SystemVerilog and/or VHDL. This includes designing and implementing RTL for DFT IP, including POST and IST. Additionally, you will be developing synthesis automation for DFT IP, which involves synthesis and timing constraints, RTL insertion, and verification. Your role will also involve owning, maintaining, extending, and enhancing existing DFT IP like LBIST. At Cadence, we are focused on hiring and developing leaders and innovators who are passionate about making an impact on the world of technology. Join us in our mission to solve challenges that others cannot.,

Posted 4 months ago

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Design Engineering Architech Cadence

3.0 - 7.0 years

0 Lacs

noida, uttar pradesh

On-site

As a member of the Cadence team, you will have the opportunity to contribute to the world of technology by designing and implementing DFT IP using Verilog/SystemVerilog and/or VHDL. Your responsibilities will include designing and implementing RTL for DFT IP, including POST and IST. You will play a key role in developing synthesis automation for DFT IP, which involves synthesis and timing constraints, RTL insertion, and verification. Additionally, you will be responsible for owning, maintaining, extending, and enhancing existing DFT IP such as LBIST. Join us in our mission to make a difference in the technology industry. Be a part of our team and help us tackle challenges that others cannot....

Posted 5 months ago

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