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Cadence Design Systems
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Design Engineering Architech

Design Engineering Architech

Cadence Design Systems

3 - 7 years

0 Lacs

karnataka

Posted:1 week ago| Platform: Shine logo

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Skills Required

verilog systemverilog vhdl rtl dft post ist synthesis automation timing constraints lbist

Work Mode

On-site

Job Type

Full Time

Job Description

As a member of the team at Cadence, you will play a key role in designing and implementing DFT IP using Verilog/SystemVerilog and/or VHDL. Your responsibilities will include: - Designing and implementing RTL for DFT IP including POST and IST - Developing synthesis automation for DFT IP, which encompasses synthesis and timing constraints, RTL insertion, and verification - Taking ownership of existing DFT IP like LBIST, maintaining, extending, and enhancing it Cadence is dedicated to tackling meaningful challenges in the world of technology, and as part of our team, you will have the opportunity to contribute to work that truly makes a difference.,

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Design Engineering Architech