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Design Engineering Architech

Design Engineering Architech

0 years

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0 Lacs

Noida Uttar Pradesh India

Posted:2 weeks ago| Platform:

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Skills Required

design engineering cadence technology dft ip verilog systemverilog vhdl synthesis automation timing constraints verification

Work Mode

On-site

Job Type

Full Time

Job Description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Design and implement DFT IP w/ Verilog/SystemVerilog and/or VHDL Design and implement RTL for DFT IP incl. POST, IST Develop synthesis automation for DFT IP including synthesis and timing constraints, RTL insertion and verification Own and maintain, extend, and enhance existing DFT IP like LBIST We’re doing work that matters. Help us solve what others can’t. Show more Show less

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Cadence

www.cadence.com

Software, Electronic Design Automation

San Jose

Approx. 8,000 Employees

188 Jobs

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