Design Engineering Architect

As a member of the team at Cadence, you will be responsible for designing and implementing DFT IP using Verilog/SystemVerilog and/or VHDL. Your role will involve creating RTL for DFT IP, including POST and IST. Additionally, you will be developing synthesis automation for DFT IP, which includes synthesis and timing constraints, RTL insertion, and verification. You will also have the opportunity to own, maintain, extend, and enhance existing DFT IP like LBIST. Qualifications required for this role: - Proficiency in Verilog/SystemVerilog and/or VHDL - Experience in designing and implementing DFT IP - Knowledge of synthesis automation for DFT IP - Familiarity with POST, IST, LBIST, synthesis, and timing constraints At Cadence, we are committed to doing work that matters and solving challenges that others may struggle with. Join us in making a significant impact on the world of technology.,