DV Engineer -GLS

0 - 7 years

0 Lacs

Posted:1 month ago| Platform: Indeed logo

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Work Mode

On-site

Job Type

Full Time

Job Description

Job Information

    Job Opening ID

    ZR_133_JOB

    Industry

    Engineering

    Date Opened

    07/05/2025

    Job Type

    Full time

    Work Experience

    5-7 years

    City

    Bangalore

    State/Province

    Karnataka

    Country

    India

    Zip/Postal Code

    560102
Key Responsibilities:
  • Develop and implement scalable UVM-based verification environments
  • Lead and execute GLS (Gate-Level Simulation)—timing-aware and glitch-sensitive validation is a core part of this role (must)
  • Perform Clock Domain Crossing (CDC) verification using industry-standard methodologies
  • Collaborate cross-functionally with RTL, DFT, and system teams for end-to-end verification closure
  • Analyze waveforms, root-cause issues, and contribute to debugging complex logic


Requirements

Required Skills:
  • Solid hands-on experience with SystemVerilog and UVM methodologies
  • Strong understanding and application of GLS (Gate-Level Simulation) techniques
  • Experience with CDC verification and asynchronous domain handling
  • Familiarity with tools such as VCS, Questa, Incisive
  • Scripting knowledge (Python, Perl, or Shell) is a plus

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