Senior RTL Design Engineer

Job Summary:

We are looking for highly skilled RTL Design Engineers with proven hands-on experience in at least three end-to-end production-grade projects. The ideal candidate should have a strong foundation in RTL coding (Verilog/SystemVerilog), with a focus on actual design rather than RTL integration, CDC, or lint activities. This is a critical role contributing to the development of complex SoCs, subsystems, or IPs.

Key Responsibilities:

• Develop synthesizable RTL for high-performance SoC, subsystem, or IP designs
  
• Contribute to architecture definition, micro-architecture design, and implementation
  
• Collaborate closely with architecture, verification, and physical design teams
  
• Own and deliver RTL blocks from spec to tape-out
  
• Ensure clean handoff of RTL to verification and synthesis
  
• Support post-silicon bring-up and debugging, if required

Mandatory Requirements:

• 5–10 years of hands-on RTL design experience in production-grade projects
  
• At least 3 full-cycle design projects (preferably SoC, subsystem, or IP level)
  
• Strong expertise in Verilog/SystemVerilog RTL coding
  
• Solid understanding of digital design principles including clocking, resets, data-path control, pipelining, etc.
  
• Exposure to design closure flow including synthesis and timing closure support

Preferred Skills:

• Familiarity with AMBA (AXI, AHB, APB) or similar interconnects
  
• Experience working in cross-functional engineering teams
  
• Good understanding of synthesis, STA, and backend interactions
  
• Strong problem-solving and debugging skills
  
• Excellent communication and documentation capabilities

Note:

Candidates with only integration, CDC, or lint backgrounds will not be considered. We’re specifically looking for hands-on RTL designers who have delivered real, production-ready logic.