Company: Eteros Technologies India Private Limited Eteros Technologies, Inc. is a Semiconductor Engineering services startup, head quartered in the heart of the Silicon Valley, San Jose, CA, USA. Eteros Technologies India Pvt Ltd is a wholly owned subsidiary offices in Bangalore, Noida, Hyderabad and Ahmedabad • Our world-wide customers are amongst The Who's who in the semiconductor industry. Eteros works not only with some of the top 20 semiconductor startups in the world but boasts of customers who are among the most respected publicly traded semiconductor companies. • Eteros engineers work on cutting edge technology nodes while working on the state-of-the art designs in the AI/ML, Datacenter, Automotive and 5G domains. Eteros engineers work with some of the brightest, innovative and successful engineers and leaders around the world. A one-of-a-kind opportunity where young Eteros engineers showcase their ability and experience world-wide from day 1 while learning from some of the world's most well-respected companies. • We are not your traditional design services company offering staff augmentation. Eteros engineers are treated as an integral part of the customer team and routinely are responsible for turnkey, end-to-end ownership and delivery, whether it is Implementation, Digital and Mixed Signal Verification, DFT or Analog Design and Layout. Eteros and our engineers work closely with our customers to define and set methodologies and design flows. • Eteros invests in our engineers. Our engineers are continuously learning, on and off the job. They are able to grow the breadth and depth of knowledge. We believe in preparing our employees for the fast-track in career development as well as longevity ----------------------------------------------------------------------------- Job Title/Role: DFT - Senior Engineer/Lead Location : Bangalore/Hyderabad/Ahmedabad Experience Level : 4+ Years Industry : Semiconductors Employment Type : Full-time Job Functions : Engineering ----------------------------------------------------------------------------- Summary Minimum 4 yrs+ experience in DFT implementation Must have worked on Scan Insertion, MBiST, ATPG, Simulations Must have experience with Synopsys DFT tools & Flows Experience in DFT timing closure preferred Experience in multi-die HBM/Memory testing with Synopsys tools preferred Work hands-on on critical tasks of DFT implementation Own the DFT implementation flows, methodologies and execution of SoCs Experience Experience in all phases of the DFT pre and post-Si for large SoCs Implement DFT of SoC/Full-chip-level and/or high-speed cores/blocks Experience in high-speed, low-power, mixed-signal SoC’s is a plus Preferably worked on 5nm/7nm/12nm/14nm/16nm nodes at the major foundries Experience in developing DFT architecture, Test-plan, implementation methodologies Experience in scan insertion, memory-BIST, JTAG/IJTAG, CTL, IEEE 1149.1/1500 wrappers, BSCAN, Compression, ATPG, Simulations, post-Si testing/debug Experience in manual test-point insertion, improve coverage targets, high-compression Experience in hierarchical ATPG, OCC/OPCG, power-aware scan/ATPG methodologies Experience in test-mode constraints generation and test-mode timing closure Experience in patter generation for foundry, post-Si support/debug Thorough understanding of digital design, timing analysis, and physical design process EDA Tools: Cadence (Encounter-Test, Modus-DFT, Tempus, Conformal), Mentor (Tessent tool suite), Synopsys (DFTC, Tetramax, TestMax-DFT, SMS, PTSI) Requirements • BTech/MTech/PhD with in Electrical or Computer engineering • 4-8years of hands-on experience with DFT and test flow with commercial EDA tools for large and complex SOCs • Strong fundamental knowledge of DFT techniques include JTAG, ATPG, yield learning, logic diagnosis, Scan compression, IEEE 1500 Std. and MBIST • Experience with Cadence & Synopsys DFT tools is required. • Strong programming skills in Perl/TCL/C++ and shell scripting is required • Must be able to solve complex problems and independently drive tasks to completion in a timely manner. • Be able to work under limited supervision and take complete accountability. • Excellent written and verbal communication skills What's in it for you • Work on leading edge technologies • An opportunity for career development and growth • Competitive compensation • Medical Benefits and more
Company: Eteros Technologies India Private Limited Eteros Technologies, Inc. is a Semiconductor Engineering services startup, head quartered in the heart of the Silicon Valley, San Jose, CA, USA. Eteros Technologies India Pvt Ltd is a wholly owned subsidiary offices in Bangalore, Noida, Hyderabad and Ahmedabad • Our world-wide customers are amongst The Who's who in the semiconductor industry. Eteros works not only with some of the top 20 semiconductor startups in the world but boasts of customers who are among the most respected publicly traded semiconductor companies. • Eteros engineers work on cutting edge technology nodes while working on the state-of-the art designs in the AI/ML, Datacenter, Automotive and 5G domains. Eteros engineers work with some of the brightest, innovative and successful engineers and leaders around the world. A one-of-a-kind opportunity where young Eteros engineers showcase their ability and experience world-wide from day 1 while learning from some of the world's most well-respected companies. • We are not your traditional design services company offering staff augmentation. Eteros engineers are treated as an integral part of the customer team and routinely are responsible for turnkey, end-to-end ownership and delivery, whether it is Implementation, Digital and Mixed Signal Verification, DFT or Analog Design and Layout. Eteros and our engineers work closely with our customers to define and set methodologies and design flows. • Eteros invests in our engineers. Our engineers are continuously learning, on and off the job. They are able to grow the breadth and depth of knowledge. We believe in preparing our employees for the fast-track in career development as well as longevity ----------------------------------------------------------------------------- Job Title/Role: Synthesis and Static Timing Analysis - Staff Design Engineer/Design Manager Location : Bangalore/Hyderabad/Ahmedabad/Noida Experience Level : 6+ Years Industry : Semiconductors Employment Type : Full-time Job Functions : Engineering ----------------------------------------------------------------------------- Summary Join a development team and lead the synthesis, static timing and DFT efforts for an advanced mixed signal chip for a high-profile Silicon Valley startup. In this highly visible role, as part of a highly talented team you will be at the heart of the Soc design effort interfacing with all disciplines with critical impact in getting functional products to of customers quickly. As a Sr, ASIC STA Engineer, you will be a part of the SOC digital design team responsible for providing integrated solutions into a growth industry Key Qualifications The position requires thorough knowledge of the ASIC design timing closure flow and methodology. • BTech/MTech/PhD with at least 6+ years hands-on experience in ASIC timing constraints generation and timing closure. • Expertise in STA tools (Tempus and Primetime) and methodologies for timing closure with a good understanding of OCV, noise and crosstalk effects on timing. • Familiarity with all aspects of timing closure of high-performance, mixed-signal SoCs in advanced finFET technology nodes, preferably 7nm. • Knowledge of timing corners/modes and process variations. • Knowledge of low-power techniques including clock gating, power gating and millivoltage designs. Proficient in scripting languages (Tcl and Perl). • ECO timing flow • Strong communication skills are a pre-requisite as the candidate will interface with a lot of different groups (e.g. digital design, verification, DFT, physical design, etc.). • Familiarity with RTL, synthesis, logic equivalence, DFT, floor-planning, and backend related methodology and tools. • Must be able to solve complex problems and independently drive tasks to completion in a timely manner. • Be able to work under limited supervision and take complete accountability. Responsibilities Include • Full chip and block level timing closure ownership throughout the entire project cycle (RTL, synthesis, and physical implementation). • Develop and maintain methodology and flows related to timing verification and closure. • Generation of block and full chip timing constraints. • Analyze timing reports and utilize scripting techniques to develop insights and drive rapid Eteros Technologies, Inc. Confidential Sep 2020 timing closure. • Support digital chip integration work and flows What's in it for you • Work on leading edge technologies • An opportunity for career development and growth • Competitive compensation • Medical Benefits and more
Eteros Technologies is looking for experienced ASIC Verification Design Engineers to join our team Looking only for Immediate joiners. We are seeking individuals with 5 to 15 years of experience to be a part of our projects, working on innovative cutting-edge technologies. Work Location: Bangalore/ Hyderabad/ Ahmedabad Experience from 5 yrs to 15 years in SoC level Verification Looking only for Immediate joiners. Proficiency in System Verilog and UVM Exposure to verifying DSP based SoC designs(with Smart Cache/TCM and Familiar with Multiply and accumulate unit ( MAC) Experience with SoC memory sub-system, LPDDR. Writing C code and working on System Verilog-C (SV-C) testbenches. Must be familiar with ARM/RISC-V subsystems. Familiar with one or more protocols like AMBA protocols, JTAG, SPI, Ethernet, UCIE etc Eteros Technologies, Inc. is a Semiconductor Engineering services startup, Founded in 2020 in Silicon Valley and led by professionals with over 150 years of combined semiconductor design experience, the Eteros team has numerous successful tape outs under its belt and a global presence of customers spanning the US, Europe and APAC. We work on cutting edge technology nodes while working on the state-of-the art designs in the AI/ML, Datacenter, Automotive and 5G domains. Kindly visit (https://www.eterostech.com/) for more details.
[{"Salary":null , "Remote_Job":false , "Posting_Title":"DSP-SoC Staff Verification Engineer" , "Is_Locked":false , "City":"Bengaluru" , "Industry":"Semiconductor" , "Job_Description":" Specialized in verifying DSP based SoC designs -Knowledge of Smart Cache/TCM -Familiar with Multiply and accumulate unit (MAC) -Understanding of SIMD on vector operation -Knowledge of IEEE fixed and floating points Must be familiar with ARM/RISC-V subsystems. Proficiency in SystemVerilog and UVM Capable of writing C code and working on SystemVerilog-C (SV-C) test-benches. Experience with SoC memory sub-system, LPDDR. Requirements Experience with standard interfaces such as JTAG, SPI, Ethernet, UCIe etc. Experience with the AMBA- AXI protocols Ability to deal with ambiguity, strong analytical and problem-solving skills. Proactive technical leadership, strong interpersonal skills and communication skills, and ability to work in effectively in a team Benefits Whats in it for you Work on leading edge technologies An opportunity for career development and growth Competitive compensation Medical Benefits and more ","Work_Experience":"10-20 years" , "Job_Opening_Name":"DSP-SoC Staff Verification Engineer" , "State":"Karnataka" , "Currency":"INR" , "Country":"India" , "Zip_Code":"560103" , "id":"665670000006927421" , "Publish":true , "Keep_on_Career_Site":false}]
[{"Salary":null , "Remote_Job":false , "Posting_Title":"Senior RTL Design Engineer" , "Is_Locked":false , "City":"Bengaluru" , "Industry":"Semiconductor" , "Job_Description":" Define micro-architecture and write detailed design specifications. Develop RTL code based on system-level specifications using Verilog, VHDL, or SystemVerilog. Implement complex digital functions and algorithms in RTL. Create and execute detailed test plans to verify RTL designs. Optimize designs for power, performance, and area (PPA) constraints. Perform simulation and debugging to ensure design correctness. Work with verification engineers to develop test benches and validate RTL against specifications. Strong understanding of digital design principles and concepts. Proficiency in writing and debugging RTL code. Experience with synthesis, static timing analysis, and linting tools. Familiarity with scripting languages such as Python, Perl, or TCL for automation. Experience in any of processor subsystem design, interconnect design, high speed IO interface design. Requirements Qualifications: Bachelor\u2019s or Master\u2019s degree in Electrical Engineering, Computer Engineering, or related field. 4-6 years of experience in RTL design and verification. Proven experience with digital logic design using Verilog, VHDL, or SystemVerilog. Experience with simulation tools such as VCS, QuestaSim, or similar. Hands-on experience with RTL design tools (e.g., Synopsys Design Compiler, Cadence Genus). Benefits What\u2019s in it for you: Work on leading edge technologies An opportunity for career development and growth Competitive compensation Exceptional benefits ","Work_Experience":"4-6 years" , "Job_Opening_Name":"Senior RTL Design Engineer" , "State":"Karnataka" , "Currency":"INR" , "Country":"India" , "Zip_Code":"560103" , "id":"665670000007068001" , "Publish":true , "Keep_on_Career_Site":false}]
[{"Salary":null , "Remote_Job":false , "Posting_Title":"Lead Memory Subsystem Design Verification Engineer (DDR / HBM)" , "Is_Locked":false , "City":"Bengaluru" , "Industry":"Semiconductor" , "Job_Description":" Proven hands-on experience verifying the digitallogic of DDR/HBM memory subsystems. Solid understanding of JEDEC specifications for LPDDRx/DDRx/HBMx Knowledge of DDR PHY interface (DFI) protocols and specifications. Familiarity with RAS (Reliability, Availability, and Serviceability) featuresin memory subsystems: Requirements Integrate and bring upVerification IPs (VIPs) such as DDR_PHY and memory models into UVMenvironments. Develop drivers, checkers, and scoreboards using SystemVerilog/UVM. Debugging, maintain regression and drive functional and code coverageclosure. Benefits Whats in itfor you Work on leading edge technologies An opportunity for career development and growth Competitive compensation Medical Benefits and more ","Work_Experience":"6-8 years","Job_Opening_Name":"Lead Memory Subsystem Design Verification Engineer (DDR / HBM)" , "State":"Karnataka" , "Currency":"INR" , "Country":"India" , "Zip_Code":"560103" , "id":"665670000007119097" , "Publish":true , "Keep_on_Career_Site":false}]
[{"Salary":null , "Remote_Job":false , "Posting_Title":"Principal Engineer- DFT" , "Is_Locked":false , "City":"Bengaluru" , "Industry":"Semiconductor" , "Job_Description":" Lead the DFT implementation of a complex SoCs Work hands-on critical tasks as and when needed Own the DFTimplementation flows, methodologies, and execution of SoCs \u25E6 \uFEFF\uFEFFExperience in all phases ofthe DFT pre- and post-Si for large SoCs \uFEFF\uFEFFImplement DFT ofSoC/Full-chip-level and/or high-speed cores/blocks \uFEFF\uFEFFExperience inhigh-speed, low-power, mixed-signal SoCs is a plus \uFEFF\uFEFFPreferably worked on5nm/7nm/12nm/14nm/16nm nodes at the major foundries \uFEFF\uFEFFExperience indeveloping DFT architecture, Test-plan, implementation methodologies \uFEFF\uFEFFExperience in scaninsertion, memory-BIST, JTAG/IJTAG, CTL, IEEE 1149.1/1500 wrappers, BSCAN, Compression, ATPG, Simulations, post-Si testing/debug \uFEFF\uFEFFExperience in manualtest-point insertion, improve coverage targets, high-compression \uFEFF\uFEFFExperience inhierarchical ATPG, OCC/OPCG, power-aware scan/ATPG methodologies \uFEFF\uFEFFExperience intest-mode constraints generation and test-mode timing closure \uFEFF\uFEFFExperience in pattergeneration for foundry, post-Si support/debug \uFEFF\uFEFFThorough understandingof digital design, timing analysis, and physical design process \uFEFF\uFEFFEDA Tools: Cadence(Encounter-Test, Modus-DFT, Tempus, Conformal), Mentor (Tessent tool suite),Synopsys (DFTC, Tetramax, TestMax-DFT, SMS, PTSI) Requirements \uFEFF\uFEFF Experienceshould be 15+ rs \uFEFF\uFEFF Proven track recordwith multiple successful final production tape outs \uFEFF\uFEFF Proven ability toindependently deliver results in a very fast-moving startup environment, beable to work hands-on as and when needed \uFEFF\uFEFF Be able to work underlimited supervision and take complete accountability. Excellent written andverbal communication skills Benefits What\u2019s in it for you: Work onleading edge technologies Anopportunity for career development and growth Competitivecompensation Exceptionalbenefits ","Work_Experience":"14-16 years" , "Job_Opening_Name":"Principal Engineer- DFT" , "State":"Karnataka" , "Currency":"INR" , "Country":"India" , "Zip_Code":"560103" , "id":"665670000006307497" , "Publish":true , "Keep_on_Career_Site":false}]
[{"Salary":null , "Remote_Job":false , "Posting_Title":"SoC Verification Engineer" , "Is_Locked":false , "City":"Bengaluru" , "Industry":"Semiconductor" , "Job_Description":" Summary: Experience in ARM based SoC Verification. Must be familiar with bus matrix (fabric) designs, ETB, NVIC and ARM subsystems. Proficiency in SystemVerilog and UVM Experience with SoC memory sub-system, bus fabric, and DDR interfacing. Experience with standard interfaces such as DMA, PWM, WDOG, Timer etc. Experience with the AMBA- AXI/APB protocols Ability to deal with ambiguity, strong analytical and problem-solving skills. Proactive technical leadership, strong interpersonal skills and communication skills, and a\u200bbility to work in effectively in a team Requirements Should have 5+ years of Experience in SoC verification Proficiency in SystemVerilog and UVM methodology Very good object-oriented programming skills Experience in verification environment development Benefits Work on leading edge technologies An opportunity for career development and growth Competitive compensation Exceptional benefits ","Work_Experience":"4-6 years","Job_Opening_Name":"SoC Verification Engineer" , "State":"Karnataka" , "Currency":"INR" , "Country":"India" , "Zip_Code":"560013" , "id":"665670000006698128" , "Publish":true , "Keep_on_Career_Site":false}]
[{"Salary":null , "Remote_Job":false , "Posting_Title":"Lead DSP- SoC Verification Engineer" , "Is_Locked":false , "City":"Bengaluru" , "Industry":"Semiconductor" , "Job_Description":" Specialized in verifying DSP based SoC designs -Knowledge of Smart Cache/TCM -Familiar with Multiply and accumulate unit (MAC) -Understanding of SIMD on vector operation -Knowledge of IEEE fixed and floating points Must be familiar with ARM/RISC-V subsystems. Proficiency in SystemVerilog and UVM Capable of writing C code and working on SystemVerilog-C (SV-C) test-benches. Experience with SoC memory sub-system, LPDDR. Requirements Experience with standard interfaces such as JTAG, SPI, Ethernet, UCIe etc. Experience with the AMBA- AXI protocols Ability to deal with ambiguity, strong analytical and problem-solving skills. Proactive technical leadership, strong interpersonal skills and communication skills, and ability to work in effectively in a team Benefits Whats in it for you Work on leading edge technologies An opportunity for career development and growth Competitive compensation Medical Benefits and more ","Work_Experience":"6-10 years","Job_Opening_Name":"Lead DSP- SoC Verification Engineer" , "State":"Karnataka" , "Currency":"INR" , "Country":"India" , "Zip_Code":"560103" , "id":"665670000007035003" , "Publish":true , "Keep_on_Career_Site":false}]
[{"Salary":null , "Remote_Job":false , "Posting_Title":"Lead / Staff Design Verification Engineer" , "Is_Locked":false , "City":"Bengaluru" , "Industry":"Semiconductor" , "Job_Description":" Requirements: Should have experience on UCIe / PCIe / CXL / Unipro / USB-2 / 3.x / MIPI ( CSI/DSI )/HDMI/Ethernet ( MAC and PCS ) /DDR/LPDDR/HBM memory protocol Experience with the AMBA- AXI/APB protocols Experience in ARM base SoC Verification is a plus Knowledge of scripting languages like Perl, Python, Tcl, shell to achieve automation of verification methodologies and flows Ability to deal with ambiguity, strong analytical and problem-solving skills. Proactive technical leadership, strong interpersonal skills and communication skills, and ability to work in effectively in a team Requirements Qualifications: Should have 8-12 years of experience in verification Proficiency in SystemVerilog and UVM methodology Very good object-oriented programming skills Experience verification environment development Experience in IP/Sub-System level verification Benefits What\u2019s in it for you: Work on leading edge technologies An opportunity for career development and growth Competitive compensation Exceptional benefits ","Work_Experience":"8-12 years" , "Job_Opening_Name":"Lead / Staff Design Verification Engineer" , "State":"Karnataka" , "Currency":"INR" , "Country":"India" , "Zip_Code":"560103" , "id":"665670000005833706" , "Publish":true , "Keep_on_Career_Site":false}]
[{"Salary":null , "Remote_Job":false , "Posting_Title":"Principal SoC-GLS Verification Engineer" , "Is_Locked":false , "City":"Bengaluru" , "Industry":"Semiconductor" , "Job_Description":" Collaborate closely witharchitecture and RTL design teams to verify functional correctness of thedesign. Develop detailed test plans and set up test environments accordingly. Assist in building and enhancing verification & GLS flows, automationscripts, and regression infrastructure. Write and implement tests using assembly, C/C++, SystemVerilog based on definedtest plans. Design and implement checkers in SystemVerilog or C-based transactors tovalidate functionality. Write assertions and apply formal verification techniques to improve designrobustness. Build and maintain test benches; generate directed and constrained-randomtests. Debug test failures, run simulations, and track down the root cause of bugs. Create and maintain coverage monitors; analyze coverage data to ensure testplan completeness. \u200b Manage verification schedules and contribute to cross-functional engineeringefforts. Requirements In-depth knowledge of digitallogic design, CPU/SoC architecture, and micro-architecture. Strong proficiency in SystemVerilog for design verification and verificationmethodologies Solid experience in Gate-Level Simulation o Zero/Unit delay bringup o Familiar with hybrid/black box methods o SDF simulations \u200b Solid experience in C/C++ programming & scripting languages such as Pythonor TCL Benefits Whats in itfor you Work on leading edge technologies An opportunity for career developmentand growth Competitive compensation Medical Benefits and more ","Work_Experience":"12-14 years" , "Job_Opening_Name":"Principal SoC-GLS Verification Engineer" , "State":"Karnataka" , "Currency":"INR" , "Country":"India" , "Zip_Code":"560103" , "id":"665670000007119253" , "Publish":true , "Keep_on_Career_Site":false}]
This position is for an Analog Layout Engineer role who should have the below required knowledge and skills - - Should have good understanding of semiconductor / Analog Layout & Physical verification basics. - Good hands-on Block level scratch Layout work, floor plan, placement, routing - Hands on in 28nm/22nm/ 14nm/ 7nm/ 5nm is desirable - Should understand Analog layout concepts on BGR / LDO/ OPAMP/ ADC/ DAC etc - Hands on Layout exposure to matching techniques like Inter-digitization and common centroid on current mirrors and differential pairs. - Should have good understanding of full custom layout implementation and Layout dependent effects - Good matching and other analog layout related concepts and hands-on implementation from scratch. - Work hands-on critical tasks as and when needed Requirements Requirements Experience: - 5 - 10 years of Analog Layout experience is required - 5nm/7nm/ 10nm/14nm/16nm with Finfet experience is a MUST. - Hands-on expertise in layout techniques such as matching / Shielding / Handling Clocks Etc - Experience in block-level floor-plan, hierarchical layout methodologies / including Power Mesh - Should have performed Physical Verification checks (DRC/LVS/DFM checks) - Experience in analyzing and resolving failure mechanisms EM/IR/ANT/DENSITY/Latch-up - Experience in Tools like Cadence-Virtuoso -XL / Calibre/ PVS/ Custom Compiler/ ICV - Strong scripting skills with Perl/Python/SKILL is a plus Benefits Benefits Whats in it for you - Work on leading edge technologies - An opportunity for career development and growth - Competitive compensation & Exceptional benefits
Porting test-case from VCS to Xcelium environment Debugging the TB issues and fix it for Xcelium Collaborate closely with architecture and RTL designteams to verify functional correctness of the design. Develop detailed test plans and set up test environments accordingly. Assist in building and enhancing verification & GLS flows, automationscripts, and regression infrastructure. Write and implement tests using assembly, C/C++, SystemVerilog based ondefined test plans. Design and implement checkers in SystemVerilog or C-based transactors tovalidate functionality. Write assertions and apply formal verification techniques to improve designrobustness. Build and maintain test benches; generate directed and constrained-randomtests. Debug test failures, run simulations, and track down causes of bugs. Create and maintain coverage monitors; analyze coverage data to ensure testplan completeness. Manage verification schedules and contribute to cross-functional engineeringefforts. Requirements In-depth knowledge of digital logic design, CPU/SoCarchitecture, and micro-architecture. Strong proficiency in SystemVerilog for design verification and verificationmethodologies Solid experience in C/C++ programming & scripting languages such asPython or TCL Good UVM skills Understanding of the complex test-benches Solid experience in Gate-Level Simulation o Zero/Unit delay bringup o Familiar with hybrid/black box methods o SDF simulations Benefits Whats in itfor you Work on leadingedge technologies An opportunityfor career development and growth Competitivecompensation Exceptionalbenefits