58 Ic Jobs

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. Aprisa offers complete functionality for top-level hierarchical design and block-level implementation for complex digital IC designs. The detail-route-centric architecture and hierarchical database enable fast design closure and optimal quality of results at a competitive runtime. This role is based in Bangalore. But you’ll also get to visit other locations in India and globe, so you’ll need to go where this job takes you. In return, you’ll get the chance to work with teams impacting entire cities, countries, and the shape of things to come. This is your role Lead a Team of Engineers working on solving the latest design challenged in Logic Synthesis Collaborate with RnD and drive the roadmap for next generation RTL2GDSII solution. Work with design community in solving critical designs problems to achieve desired performance, area and power targets. Deployment of Synthesis solution with various customers working on cutting edge technologies (7nm and forward). Develop & deploy training and technical support to customers using Siemens EDA tools. We don’t need superheroes, just superminds! Typically requires minimum of 9+ years of experience in Logic Synthesis flows Proficiency in Verilog, System Verilog & VHDL. Strong knowledge of RTL2GDSII flow with strong fundamentals in digital design & implementation. Prior experience in IC digital design flows and front-end EDAT tools including Synthesis, DFT, Formal Verification, Logic Equivalence Checks Hands-on experience using commercial synthesis tools like Synopsys-DC/FC, Cadence-Genus is a must. Experience with advance technology nodes 7nm and below. Hands-on experience in debug & deliver solutions to critical design issues related to synthesis. TCL, Perl or Python scripting is a plus. Self-motivated team player with a zeal to drive high team performance. Good problem solving and debugging skills. Strong verbal & written communication skills We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, variable pay, other benefits, pension, healthcare and actively support working from home. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. Transform the everyday #LI-EDA #LI-Hybrid

B.E.- E.C. / Electrical Engineer with Minimum 1 to 3 Years of experience in programming of Automation products like PLC-HMI-SCADA-SERVO. Full knowledge of PLC-HMI-IOs-Communication protocol-Drives-Servo Motors with programming activity. Required Candidate profile Good knowledge of control panel wiring for service operation and can understand control wiring scheme. Ready to travel for program and service purpose at customer site. Perks and benefits Negotiable - Depending Upon Candidate & Experience

Diploma / B.E.- E.C. / I.C. / E.E. with 0 to 3 Years in Industrial Automation Products. Candidate should have well Experience of PLC Programming, HMI, VFD, SCADA. Looking after working of machine (Erection). PLC Programming, HMI, SCADA development. Required Candidate profile Timely solve break down of machines & troubleshooting if required. Cabling & testing of machinery. Visit sites for solving queries / implementation / commissioning of machineries. M - 9377865778 Perks and benefits Negotiable - Depending Upon Candidate & Experience

Job Track Description: The ETL Data Architect would be responsible for driving data migration strategy and execution within complex Enterprise landscape. This role will be responsible to bring in the best practices of data migration and integrations with Salesforce. Bring in best practices for Salesforce data migration integration. Create Data migration strategy for Salesforce implementations. Define template/uniform file format for migrating data into Salesforce. Must Skill: Data Architect with 8-10 years of ETL experience and 5+ years of Informatica Cloud (IICS, ICRT) experience. 5+ years of experience on Salesforce systems. Develop comprehensive data mapping and transformation plans to align data with Salesforce data model and software solution. Good understanding of Salesforce data model and schema builder. Excellent understanding of relational database concepts and how to best implement database objects in the Salesforce. Experience integrating large sets of data into Salesforce from multiple data sources. Experience with EDI transactions. Experience in Design and Development of ETL/Data Pipelines. Excellent understanding of SOSL and SOQL and the Salesforce Security model. Full understanding of project life cycle and development methodologies. Ability to interact with technical and functional teams. Excellent oral, written communication and presentation skills. Should be able to work in offshore / onsite model. Experience: Expert in ETL development with Informatica cloud using various connectors. Experience with Real Time integrations and Batch scripting. Expert in implementing the business rules by creating various transformations, working with multiple data sources like flat files, relational and cloud database, etc. and developing mappings. Experience in using ICS workflow tasksSession, Control Task, Command tasks, Decision tasks, Event wait, Email tasks, Pre-sessions, Post-session, and Pre/Post commands. Ability to migrate objects in all phases (DEV, QA/UAT and PRD) following standard defined processes. Performance analysis with large data sets Experience in writing technical specifications based on conceptual design and stated business requirements. Experience in designing and maintaining logical and physical data models and communicates to peers and junior associates using flowcharts, unified data language, Data flow Diagram. Good Knowledge of SQL, PL/SQL and Data Warehousing Concepts. Experience in using Salesforce SOQL is a plus. Responsibilities: Excellent troubleshooting and debugging skills in Informatica Cloud. Significant knowledge of PL/ SQL including tuning, triggers, ad hoc queries, and stored procedures. Strong analytical skills. Works under minimal supervision with some latitude for independent judgement. Prepare and package scripts and code across development, test, and QA environments. Participate in change control planning for production deployments. Conducts tasks and assignments as directed.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Working experience (2+ years) in preferably Memory design Compiler approach of developing embedded SRAM/ROM development Fundamental know how on bit cell and its characteristics (SNM, WM, Cell current, Standby current, data retention) Fundamentals of process variability and its effect on memory design Strong understanding of Digital/Memory circuit design/layouts Critical path modeling concept, various type of models ( RC, C, Pai, ladder, distributive, etc) Good knowledge of semiconductor physics in general. Knowledge of and affinity to IC technology and IP design is mandatory

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Job Summary: As a Staff/Senior Staff SoC Physical Verification Engineer, you will be responsible for leading and executing full-chip and block-level physical verification (PV) for advanced SoC designs. You will collaborate with cross-functional teams to ensure design integrity, manufacturability, and compliance with foundry rules across multiple technology nodes (e.g., 7nm, 5nm, 3nm). Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Key Responsibilities: Own and drive physical verification (LVS, DRC, ERC, PERC, Antenna, DFM) at block and top levels. Collaborate with Physical Design (PD), RTL, and CAD teams to resolve PV issues and ensure sign-off quality. Analyze and debug PV violations using tools like Calibre, ICV, and IC Validator. Work on ESD routing, bump/RDL planning, and padring integration. Develop and refine PV flows and methodologies in collaboration with CAD teams. Mentor junior engineers and lead PV closure for complex SoC programs. Interface with foundries for rule deck updates and tapeout readiness. Required Skills & Qualifications: B.E./B.Tech or M.E./M.Tech in Electronics, VLSI, or related field. 7"“14 years of hands-on experience in SoC physical verification. Strong expertise in Calibre, ICV, ICC2, Fusion Compiler, and Innovus. Deep understanding of DRC, LVS, ERC, PERC, Antenna, and density checks. Experience with advanced nodes (7nm and below) and FinFET technologies. Familiarity with scripting (TCL, Perl, Python) for automation and debugging. Exposure to ESD, latch-up, IR drop, and EM analysis. Excellent problem-solving, communication, and leadership skills. Preferred Qualifications: Experience with Intel, TSMC, or Samsung foundry rule decks. Knowledge of RTL-to-GDSII flow and ECO implementation. Prior experience in customer-facing or cross-site collaboration roles.

Job Area: Engineering Group, Engineering Group > Software Engineering General Summary: Qualcomm ADAS/Autonomy team is engaged in offering optimized solutions built on DSP, computer vision and machine learning algorithms for the Qualcomm ADAS/Autonomy SoCs. We are seeking engineers with experience in system and SoC SW level functional safety concepts. The job requires understanding and defining of the Safety Concept and Architecture, Software Safety requirements, defining and deploying safety processes and development of Safety software by following the ISO26262 software processes. Interaction with customers, architects and test/integration teams are required as part of the job. The job also involves working with the Software quality team for adherence of ISO26262 and ASPICE processes. In this role, the candidate will work with local and global teams to understand, define and implement and productize Automotive specific features including software enablement (drivers/BSP/RTOS/AUTOSAR MCAL), security, functional safety, and power applied to Automotive products on our current and next generation SoCs. The candidate will also have the responsibility to coordinate and execute plans which will encompass validation of all the feature requirements. The Candidate will have the responsibility to identify and address any abnormal discoveries by root-causing and providing detailed corrective actions in the form of optimizations and/or fixes. When possible, the candidate is expected to prototype and pre-validate recommended fixes. Additionally, the candidate will be responsible for any automation of design under test along with validation efforts and working closely with design/production/bench IP teams. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Software Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of Software Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 1+ year of Software Engineering or related work experience. 2+ years of academic or work experience with Programming Language such as C, C++, Java, Python, etc. 3-6 years of Embedded Software Development experience, including low level drivers, and RTOS The candidate should possess 3 to 6 years of industry experience in embedded software driver development and having expertise in one or more below areas would be preferred: Should be able to ramp up fast and must have the attitude to work with the team. Strong C and Assembly Programming with OS & Multi-Processor concepts Embedded software development in C and C++ on ARM or similar cores. Hands on experience of driver development on any RTOS, Experience in SafeRTOS/FreeRTOS based development is nice to have Experience in Autosar MCAL development is nice to have Experience in Autosar BSW integration and validation is nice to have ARM Trust-Zone & ARMv7/v8 architecture. Good debugging skills with experience on debugging with Lauterbach JTAG debuggers. Work on challenging customer requirements and issues. Basic understanding one or more of hardware blocks - Clocks, PLLs, GPIO, Interrupt Controllers (GIC), Peripherals (SPI/I2C/UART/CAN/Ethernet/Clock/etc) Automotive SW development experience is must have Experience in ISO26262/functional safety and ASPICE is highly desirable Basic knowledge on Power Mgmt. IC is desirable Knowledge of Software/Hardware Security concepts is desirable Closely work with the hardware team to contribute/suggest modifications to the hardware design. Any past working experience on Qualcomm chips nice to have

Job Area: Engineering Group, Engineering Group > Software Engineering General Summary: Qualcomm ADAS/Autonomy team is engaged in offering optimized solutions built on DSP, computer vision and machine learning algorithms for the Qualcomm ADAS/Autonomy SoCs. We are seeking engineers with experience in system and SoC SW level functional safety concepts. The job requires understanding and defining of the Safety Concept and Architecture, Software Safety requirements, defining and deploying safety processes and development of Safety software by following the ISO26262 software processes. Interaction with customers, architects and test/integration teams are required as part of the job. The job also involves working with the Software quality team for adherence of ISO26262 and ASPICE processes. In this role, the candidate will work with local and global teams to understand, define and implement and productize Automotive specific features including software enablement (drivers/BSP/RTOS/AUTOSAR MCAL), security, functional safety, and power applied to Automotive products on our current and next generation SoCs. The candidate will also have the responsibility to coordinate and execute plans which will encompass validation of all the feature requirements. The Candidate will have the responsibility to identify and address any abnormal discoveries by root-causing and providing detailed corrective actions in the form of optimizations and/or fixes. When possible, the candidate is expected to prototype and pre-validate recommended fixes. Additionally, the candidate will be responsible for any automation of design under test along with validation efforts and working closely with design/production/bench IP teams. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Software Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of Software Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 1+ year of Software Engineering or related work experience. 2+ years of academic or work experience with Programming Language such as C, C++, Java, Python, etc. 3-6 years of Embedded Software Development experience, including low level drivers, and RTOS The candidate should possess 3 to 6 years of industry experience in embedded software driver development and having expertise in one or more below areas would be preferred: Should be able to ramp up fast and must have the attitude to work with the team. Strong C and Assembly Programming with OS & Multi-Processor concepts Embedded software development in C and C++ on ARM or similar cores. Hands on experience of driver development on any RTOS, Experience in SafeRTOS/FreeRTOS based development is nice to have Experience in Autosar MCAL development is nice to have Experience in Autosar BSW integration and validation is nice to have ARM Trust-Zone & ARMv7/v8 architecture. Good debugging skills with experience on debugging with Lauterbach JTAG debuggers. Work on challenging customer requirements and issues. Basic understanding one or more of hardware blocks - Clocks, PLLs, GPIO, Interrupt Controllers (GIC), Peripherals (SPI/I2C/UART/CAN/Ethernet/Clock/etc) Automotive SW development experience is must have Experience in ISO26262/functional safety and ASPICE is highly desirable Basic knowledge on Power Mgmt. IC is desirable Knowledge of Software/Hardware Security concepts is desirable Closely work with the hardware team to contribute/suggest modifications to the hardware design. Any past working experience on Qualcomm chips nice to have

1. Hands on work on custom layout for analog blocks like High Speed SerDes and General purpose IO designs with Cadence Virtuoso on latest technologies like 5nm and below and also take leadership roles in delivery of IPs 2. Work on Floor planning, power design, signal routing strategy, EMIR awareness andparasitic optimisations 3. Understand and apply analog Layout techniques to ensure the design meets performance with minimum possible area and good yield. 4. Participate in building and enhancing layout flow for faster, higher quality design process. 5. Checking physical verifications like DRC/LVS/ERC/ANT/DFM and other IBM internal checks 6. Collaborate with Circuit Designers to solve challenging problems 7. Writing /PYTHON scripts to automate repetitive tasks 8. Work with Place and Route engineer to integrate custom macros into top level. 9. Able to perform design reviews across global team 10. Work closely with required global teams to ensure the success of the whole product. 11. Leadership in delivery of macros we plan to own from India Job requirements: 1. Experience in doing layouts for analog blocks like SerDes, ADCs, DACs, LDOs, PLLs, BGAP & amplifiers etc. 2. Experience in designing layouts for high-speed circuits is a plus. 3. Layout experience in the following technology nodes3nm, 5nm and 7nm FinFET. 4. Good team worker with multi-discipline, multi-cultural and multi-site environments 5. Strong fundamental knowledge in semiconductor device physics, layout principles, IC reliability and failure mechanisms6. Good problem-solving skills are essential where problems are analysed upfront, identifying gaps, and providing optimum solutions7. Knowledge in Skill/perl/tcl/Python scripting is a plus. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise The Analog layout design engineer with experience in next generation Ultra high speed serial IO link (HSS) interface for Cognitive, ML,DL, and data center applications. The engineer needs to have knowledge in the design and development full custom analog layouts for ultra high speed 32G/50G/112G IO link interfaces. Preferred technical and professional experience Experience in 3,5,7,14 nm analog layout design. Working on Cutting edge technology and HSS domain . Quick learner, deep layout design knowledge, problem solving skills and good communication skills with cross teams across the Geos.

Primary Skills: Support during the investigation of suspected cyber security events Analysis and respond to the service request and incident related to securitytools (Carbon Black,Armis, EDR,etc) and related policies Deep knowledge of TCP/IP suite and ICS protocols. Endpoint Detection Response (Carbon Black, CrowdStrike) Hands on Experience in Cyberark Responsibilities: Supports Carbon Black Endpoint Detection and Response (EDR) applications and ensures cyber security service availability for the endpoints. Daily monitoring EDR AV logs Monitor EDR dashboard for compliance, threats and further troubleshootingwherever required. Basic level of fine tune policies. Raise case and follow up with Vendor support for any issue. Maintain security Run Books and SOPs. Ticket handling Generate regular reports and updates on security incident trends. Monitoring Incidents/Outages Carbon Blac. Primary Skills: Support during the investigation of suspected cyber security events Analysis and respond to the service request and incident related to security tools (Carbon Black, Armis, EDR, etc) and related policies Deep knowledge of TCP/IP suite and ICS protocols. Endpoint Detection Response (Carbon Black, CrowdStrike) Hands on Experience in Cyberark. Responsibilities: Supports Carbon Black Endpoint Detection and Response (EDR) applications and ensures cyber security service availability for the endpoints. Daily monitoring EDR AV logs Monitor EDR dashboard for compliance, threats and further troubleshooting wherever required. Basic level of fine tune policies. Raise case and follow up with Vendor support for any issue. Maintain security Run Books and SOPs. Ticket handling Generate regular reports and updates on security incident trends. Monitoring Incidents/Outages

Part of a Assembly Test operations group such as debugging test program and yield enhancement activities. Opportunity to participate and drive revenue improvement projects. External interface and program / product discussion with Customers. Device and test software and hardware first level troubleshooting. Trouble shooting of Electronics and Mechanical Equipments. Break down maintenance. Requirements Diploma in Electronics Communications / Mechanical or equivalent. Direct experience in any ATE and IC Test Methodology. Experience in IC ATE test program debugging is highly desired. Familiar with measurement tools like spectrum analyzers, oscilloscopes or vector analyzers is a strong advantage. Able to work under minimal supervision or good project management and reporting skills. Bottom-line driven, good interpersonal skills and experience in cross-functional. Good Communication skills Able to multi-task on multiple projects and execute well in pressure situation.

Part of a Assembly Test operations group such as debugging test program and yield enhancement activities. Opportunity to participate and drive revenue improvement projects. External interface and program / product discussion with Customers. Device and test software and hardware first level troubleshooting. Trouble shooting of Electronics and Mechanical Equipments. Break down maintenance. Requirements Diploma in Electronics Communications / Mechanical or equivalent. Direct experience in any ATE and IC Test Methodology. Experience in IC ATE test program debugging is highly desired. Familiar with measurement tools like spectrum analyzers, oscilloscopes or vector analyzers is a strong advantage. Able to work under minimal supervision or good project management and reporting skills. Bottom-line driven, good interpersonal skills and experience in cross-functional. Good Communication skills Able to multi-task on multiple projects and execute well in pressure situation.

Part of an expert team to provide process support in Assembly operation such as debugging the controller program and yield enhancement activities. Opportunity to participate and drive revenue improvement projects. External interface and program / product discussion with Customers. Device and hardware first level troubleshooting. Coach PE/EE on technical soft skills development. Requirements Degree in Mechanical Engineering or equivalent. Direct experience in any ATE and IC Test Methodology. Experience in IC ATE test program debugging is highly desired. Familiar with measurement tools like spectrum analyzers, oscilloscopes or vector analyzers is a strong advantage. Able to work under minimal supervision or good project management and reporting skills. Bottom-line driven, good interpersonal skills and experience in cross-functional. Good Communication skills Able to multi-task on multiple projects and execute well in pressure situation.

Responsible to resolve all equipment related problems pertaining to Assembly Test. Ensure minimum down time to achieve the targeted production volumes within the stipulated timeframe. Analyze the machine down time trends, in co-ordination with relevant functions for continual improvement. Plan and execute preventive maintenance activities for all assembly related equipment and accessories. Maintain and adhere the preventive maintenance schedule keep updating the records Responsible for Calibration of all test measuring equipment, gauges and instruments Lead the design and development team and to take care of all design and developmental activities, including possible indigenous spare development, of pertaining to assembly and process equipment / accessories. Co-ordinate with relevant functions in the finalization and execution of new projects. Requirements Degree in Electronic Communication or Instrumental Engineering or equivalent. Minimum 2~3 years of experience in IC Assembly and Packaging technology Able to work under minimal supervision or good project management and reporting skills Self-driven and ability to work with quick pace environment and pressure from internal and customer demands Good communication, Interpersonal skills and Problem solving skills are desirable Able to multi-task on multiple projects and execute well in pressure situation.

We are seeking a talented and detail-oriented Physical Backend Design Engineer to join our IC (Integrated circuit) development team. The role involves key aspects of physical design, including automated place and route, floorplanning, clock tree synthesis (CTS), static timing analysis (STA), power analysis, and physical verification (DRC/LVS). The ideal candidate will have a strong knowledge of physical design methodologies, experience with industry-standard tools, and a passion for delivering high-quality semiconductor solutions. You have: Bachelor s Degree in Electrical Engineering, Computer Engineering, or a related field (Master s preferred) 3+ years of experience in physical backend design for ICs. Complex chip designs through all stages of physical implementation Experience with tape-out of designs for advanced nodes is highly desirable Strong knowledge of physical design concepts, including place and route (PnR), clock tree synthesis (CTS), static timing analysis (STA) and power grid design Experience with physical verification tools like Cadence Pegasus or Mentor Calibre Familiarity with parasitic extraction tools (e.g., StarRC, Quantus, Calibre xRC) Scripting skills in Python, Tcl, Perl, or Shell for automation Required Tools: Cadence Innovus, Cadence Quantus, Cadence Tempus, Cadence Pegasus suite It would be nice if you also had: Experience with advanced process nodes (e.g., 7nm and below) Knowledge of low-power design techniques, such as multi-Vt, multi-Vdd, or clock gating Familiarity with DFT concepts and tools, Chip packaging and thermal analysis considerations, FinFET technology and 3D IC design methodologies Perform floorplanning, partitioning, and optimization to achieve area, power, and performance targets. Execute automated place and route (PnR) using industry-standard tools to generate physical layouts. Implement clock tree synthesis (CTS), ensuring low skew and efficient clock distribution. Conduct static timing analysis (STA) to verify timing closure and ensure the design meets performance requirements. Perform power analysis, including IR drop and electromigration (EM) checks, to optimize power distribution networks. Conduct physical verification tasks, including design rule checks (DRC) and layout vs. schematic (LVS) checks, to ensure manufacturability and compliance with foundry standards. Collaborate with design, verification, and DFT teams to resolve physical design challenges and improve chip performance. Work closely with foundry teams to address process technology issues and implement best practices.

We are seeking a talented and detail-oriented Physical Backend Design Engineer to join our IC (Integrated circuit) development team. The role involves key aspects of physical design, including automated place and route, floorplanning, clock tree synthesis (CTS), static timing analysis (STA), power analysis, and physical verification (DRC/LVS). The ideal candidate will have a strong knowledge of physical design methodologies, experience with industry-standard tools, and a passion for delivering high-quality semiconductor solutions. You have: Bachelor s Degree in Electrical Engineering, Computer Engineering, or a related field (Master s preferred) 3+ years of experience in physical backend design for ICs. Complex chip designs through all stages of physical implementation Experience with tape-out of designs for advanced nodes is highly desirable Strong knowledge of physical design concepts, including place and route (PnR), clock tree synthesis (CTS), static timing analysis (STA) and power grid design Experience with physical verification tools like Cadence Pegasus or Mentor Calibre Familiarity with parasitic extraction tools (e.g., StarRC, Quantus, Calibre xRC) Scripting skills in Python, Tcl, Perl, or Shell for automation Required Tools: Cadence Innovus, Cadence Quantus, Cadence Tempus, Cadence Pegasus suite It would be nice if you also had: Experience with advanced process nodes (e.g., 7nm and below) Knowledge of low-power design techniques, such as multi-Vt, multi-Vdd, or clock gating Familiarity with DFT concepts and tools, Chip packaging and thermal analysis considerations, FinFET technology and 3D IC design methodologies Perform floorplanning, partitioning, and optimization to achieve area, power, and performance targets. Execute automated place and route (PnR) using industry-standard tools to generate physical layouts. Implement clock tree synthesis (CTS), ensuring low skew and efficient clock distribution. Conduct static timing analysis (STA) to verify timing closure and ensure the design meets performance requirements. Perform power analysis, including IR drop and electromigration (EM) checks, to optimize power distribution networks. Conduct physical verification tasks, including design rule checks (DRC) and layout vs. schematic (LVS) checks, to ensure manufacturability and compliance with foundry standards. Collaborate with design, verification, and DFT teams to resolve physical design challenges and improve chip performance. Work closely with foundry teams to address process technology issues and implement best practices.

We are seeking a talented and detail-oriented Physical Backend Design Engineer to join our IC (Integrated circuit) development team. The role involves key aspects of physical design, including automated place and route, floorplanning, clock tree synthesis (CTS), static timing analysis (STA), power analysis, and physical verification (DRC/LVS). The ideal candidate will have a strong knowledge of physical design methodologies, experience with industry-standard tools, and a passion for delivering high-quality semiconductor solutions. You have: Bachelor s Degree in Electrical Engineering, Computer Engineering, or a related field (Master s preferred) 3+ years of experience in physical backend design for ICs. Complex chip designs through all stages of physical implementation Experience with tape-out of designs for advanced nodes is highly desirable Strong knowledge of physical design concepts, including place and route (PnR), clock tree synthesis (CTS), static timing analysis (STA) and power grid design Experience with physical verification tools like Cadence Pegasus or Mentor Calibre Familiarity with parasitic extraction tools (e.g., StarRC, Quantus, Calibre xRC) Scripting skills in Python, Tcl, Perl, or Shell for automation Required Tools: Cadence Innovus, Cadence Quantus, Cadence Tempus, Cadence Pegasus suite It would be nice if you also had: Experience with advanced process nodes (e.g., 7nm and below) Knowledge of low-power design techniques, such as multi-Vt, multi-Vdd, or clock gating Familiarity with DFT concepts and tools, Chip packaging and thermal analysis considerations, FinFET technology and 3D IC design methodologies Perform floorplanning, partitioning, and optimization to achieve area, power, and performance targets. Execute automated place and route (PnR) using industry-standard tools to generate physical layouts. Implement clock tree synthesis (CTS), ensuring low skew and efficient clock distribution. Conduct static timing analysis (STA) to verify timing closure and ensure the design meets performance requirements. Perform power analysis, including IR drop and electromigration (EM) checks, to optimize power distribution networks. Conduct physical verification tasks, including design rule checks (DRC) and layout vs. schematic (LVS) checks, to ensure manufacturability and compliance with foundry standards. Collaborate with design, verification, and DFT teams to resolve physical design challenges and improve chip performance. Work closely with foundry teams to address process technology issues and implement best practices.

We are seeking a talented and detail-oriented Physical Backend Design Engineer to join our IC (Integrated circuit) development team. The role involves key aspects of physical design, including automated place and route, floorplanning, clock tree synthesis (CTS), static timing analysis (STA), power analysis, and physical verification (DRC/LVS). The ideal candidate will have a strong knowledge of physical design methodologies, experience with industry-standard tools, and a passion for delivering high-quality semiconductor solutions. You have: Bachelor s Degree in Electrical Engineering, Computer Engineering, or a related field (Master s preferred) 3+ years of experience in physical backend design for ICs. Complex chip designs through all stages of physical implementation Experience with tape-out of designs for advanced nodes is highly desirable Strong knowledge of physical design concepts, including place and route (PnR), clock tree synthesis (CTS), static timing analysis (STA) and power grid design Experience with physical verification tools like Cadence Pegasus or Mentor Calibre Familiarity with parasitic extraction tools (e.g., StarRC, Quantus, Calibre xRC) Scripting skills in Python, Tcl, Perl, or Shell for automation Required Tools: Cadence Innovus, Cadence Quantus, Cadence Tempus, Cadence Pegasus suite It would be nice if you also had: Experience with advanced process nodes (e.g., 7nm and below) Knowledge of low-power design techniques, such as multi-Vt, multi-Vdd, or clock gating Familiarity with DFT concepts and tools, Chip packaging and thermal analysis considerations, FinFET technology and 3D IC design methodologies Perform floorplanning, partitioning, and optimization to achieve area, power, and performance targets. Execute automated place and route (PnR) using industry-standard tools to generate physical layouts. Implement clock tree synthesis (CTS), ensuring low skew and efficient clock distribution. Conduct static timing analysis (STA) to verify timing closure and ensure the design meets performance requirements. Perform power analysis, including IR drop and electromigration (EM) checks, to optimize power distribution networks. Conduct physical verification tasks, including design rule checks (DRC) and layout vs. schematic (LVS) checks, to ensure manufacturability and compliance with foundry standards. Collaborate with design, verification, and DFT teams to resolve physical design challenges and improve chip performance. Work closely with foundry teams to address process technology issues and implement best practices.

Post Silicon Validation Engineer Experience3 to 5 Years QualificationB.E / B. Tech / M.E / M. Tech Essential Duties & Responsibilities: Experience in silicon lab validation for power management ICs. Experience with validation of Mixed-signal ICs. Experience in validation test planning, test development, execution, debug and report preparation. Hands-on experience of using lab equipment such as oscilloscope, signal analyzer, signal generator, etc. familiarity of programming and scripting languages like Python, Perl Experience in automation using NI Labview is an advantage Understanding of power management ICs, architecture, specifications interpretation is required Debug skills to zero in on an issue, coordination with cross-functional teams is required Skills Experience LabVIEW, PMIC, Post Silicon Validation, System Validation, Testing Validation Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore USATexas Location - Bengaluru,Chennai,Hyderabad,Noida

Who We Are Applied Materials is the global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service cutting-edge equipment that helps our customers manufacture display and semiconductor chips- the brains of devices we use every day. As the foundation of the global electronics industry, Applied enables the exciting technologies that literally connect our world- like AI and IoT. If you want to work beyond the cutting-edge, continuously pushing the boundaries of"science and engineering to make possible"the next generations of technology, join us to Make Possible® a Better Future. What We Offer Location: Bangalore,IND At Applied, we prioritize the well-being of you and your family and encourage you to bring your best self to work. Your happiness, health, and resiliency are at the core of our benefits and wellness programs. Our robust total rewards package makes it easier to take care of your whole self and your whole family. Were committed to providing programs and support that encourage personal and professional growth and care for you at work, at home, or wherever you may go. Learn more about our benefits . Youll also benefit from a supportive work culture that encourages you to learn, develop and grow your career as you take on challenges and drive innovative solutions for our customers."We empower our team to push the boundaries of what is possible"”while learning every day in a supportive leading global company. Visit our Careers website to learn more about careers at Applied. About Applied Applied Materials is the leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. Our expertise in modifying materials at atomic levels and on an industrial scale enables customers to transform possibilities into reality. At Applied Materials, our innovations make possible the technology shaping the future. Applied Materials India is looking for an Application Engineer to join our team on Yi eld Technology Group ( YTG ). YTG is an innovative platform that develops and produces high-precision electron optical devices (electron microscopes) and advanced test systems utilizing e-beam technology for display and semiconductor advanced packaging industry. YTG is working in an internationally networked setup, with system platform design and e-beam technology development being aligned between multiple development sites located in Germany, Taiwan, and India, and with its manufacturing located in Taiwan and Germany (but with a global sourcing approach), to best serve our customers located in Asia, the USA and Europe." Roles and Responsibility Understand and translate market requirement to product spec ifications. Work with algorithm, system, software and other cross functional teams to analyze alternative solutions and provide data for decision making. Tool performance with gap/ limitation analysis to create new methodologies in order to optimize system performance for specific application . Support customer & field issues driving demos and adoption of developed tools/ features. Qualifications Master/Integrated Dual Degree/PhD scholars from premier academic institutions with 2-4 years experience, specialization in Materials Engineering/Microelectronics/Chemical Engineering/Engineering Physics / Mechatronics Our Ideal Candidate Sound fundamentals of semiconductor device physics and process knowledge (deposition, etching, etc.) Requires 70% travel on short notice to leading semiconductor chip manufacturing fabs overseas and Applied Materials headquarters Detail oriented, with strong analytical skill, problem solving and excellent communication skills, strive to get to the deep technical details Collaborate with cross-functional teams, strong documentation and presentation skill. Additional Qualifications F amiliarity of working in a semiconductor fab and experience in interfacing with field support engineers is highly desirable. Understanding of Metrology process and requirements in IC manufacturing is highly desirable. Good programming skills and hands on experience in Python. ML/DL knowledge will be an advantage. Additional Information Time Type: Full time Employee Type: Assignee / Regular Travel: Yes, 25% of the Time Relocation Eligible: Yes Applied Materials is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, ancestry, religion, creed, sex, sexual orientation, gender identity, age, disability, veteran or military status, or any other basis prohibited by law.

Project Role : Engineering Services Practitioner Project Role Description : Assist with end-to-end engineering services to develop technical engineering solutions to solve problems and achieve business objectives. Solve engineering problems and achieve business objectives using scientific, socio-economic, technical knowledge and practical experience. Work across structural and stress design, qualification, configuration and technical management. Must have skills : Manufacturing Design & Engineering Solutions Good to have skills : NAMinimum 2 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As an Engineering Services Practitioner, you will assist with end-to-end engineering services to develop technical engineering solutions, solve problems, and achieve business objectives. You will work across structural and stress design, qualification, configuration, and technical management, utilizing scientific, socio-economic, technical knowledge, and practical experience. Roles & Responsibilities- 3-6 Years of experience in the field of General Assembly (TCF). Experience in Digital manufacturing tools (3D Experience /DELMIA V5/Team center visualization/Human Jack/ Process Simulate/IC.IDO/Unity/VR/FAPLIS/Micro station etc.)- Assembly process planning, documentation & issue resolution - Assembly equipment design, planning, installation & commissioning- Physical ergonomic Assessment in production plant- Problem Solving & Project Management- C#/Python/Powerbi - Designing small Jigs & Fixtures- Executing new vehicle program projects.- Conduct dynamic and static clearance analysis studies for Cars using 3D Experience - Conduct ergonomic studies using 3D Experience - Virtual validation of plant tools Professional & Technical Skills: - Must To Have Skills: Proficiency in Manufacturing Design & Engineering Solutions.- Strong understanding of engineering principles and practices.- Experience in utilizing CAD software for design and analysis.- Knowledge of material selection and manufacturing processes. Additional Information:- The candidate should have a minimum of 3 years of experience in Manufacturing Design & Engineering Solutions.- This position is based at our Bengaluru office.- A 15 years full-time education is required. Qualification 15 years full time education

Role & responsibilities Job Title: Mix Signal ASIC/IC Functional safety engineer/manager Job location: Bangalore Work mode: Hybrid Mode of employment: Permanent / Direct Company Payroll OVERVIEW: Seeks a dynamic and experienced Mix Signal ASIC/IC Functional Safety Engineer & Manager to join the Sensor Global Quality Engineering Center within its Sensors Quality Organization. This role focuses on ensuring the compliance to Functional Safety requirements of sensor products from project definition to production release for Automotive and Industrial & Transportation (ICT) markets. This role will engage with various Engineering Centers of Expertise and manufacturing plant globally. It is a strategic role to support Sensor Technology roadmap based in our growing Global Design Center Bangalore India. KEY RESPONSIBILITIES: Functional Safety for New Technology Development: Ensure that functional safety requirements are met from project definition to production launch according to company stage gate procedure. Provide guidance to project stakeholders to adhere to ISO26262 standards Negotiate and mutually agree on required safety goals with customers (DAI) Contribute to the development of technical safety Concepts per ISO26262. Deliver Functional safety Work Products as per ISO26262 such as Safety Plan, HARA, FSR/C, TSR/C, FMEDA at hardware level (IP block/Gate). Review gate exits and release Functional Safety documentation (Safety Case) to enable production launch. YOU MUST HAVE Functional Safety Certification Experience: Minimum of 10 Years Experience in functional safety at hardware level SoC, ASIC, IC Successful release in production of project of at least ASIL C level . Proficiency with all Functional Safety tools from safety plan to safety case, including SPFM, LFM metrics Master FDMEA and FIT calculation Knowledge of Quality Standards: Familiarity with ISO 9001, AS 9100, IATF 16949 Strong English communication skills Customer & Leadership Engagement: Ensure efficient communication with customers and leadership team on functional safety related topics Anticipate and manage escalations effectively. Process & Continuous Improvement Management: Inspire a Zero-Defect mindset by ensuring data-driven problem-solving and improvement initiatives. Evaluate project outcomes, identify areas for improvement, and suggest enhancements to processes. WE VALUE Six Sigma Green Belt or Black Belt certification Experience in Cybersecurity ISO 27001 or ISO/SAE 21434 Experience participating to VDA audits, IATF audits EDUCATION Bachelor or Master in Engineering or related discipline Interested candidate please apply here. Also share your profile to chidananda@manpower.co.in; Best Regards, HR Team, Manpower Group Preferred candidate profile

Hi, We have a vacancy in Hyderabad for INVESTMENT SPECIALIST - Leading Bank Grade: Senior Manager or AVP CTC up to 20Lacs fixed Looking for profiles from: Sales or Investment background from banking/fund houses. Job Role: Ownership of the Investments target of the Branch Banking channel mapped to Increase the Mutual Fund AUM for the mapped Area Penetration of client base for creating new investors in MF / investments from existing client base Increase in (investments products) productivity of Phone Banking officers Acquisitions (NTB) attributed to presence of IC i.e NTB opened by officers on the back of investments due to the presence of the IC Other Key areas to be done periodically Officers training Driving business /coordinating with Sr. RCMS /National Head Client coverage / joint phone calls Portfolio construction and reviews are done periodically by self and team Training & Development for new joiners for better performance Process adherence Dynamic person who can think and implement new strategies for customer acquisition, penetration and retention. Job Requirements 8-10 years work experience in NBFC, Banks, Mutual Fund industry In depth domain knowledge of Mutual Fund investments in detail, PMS Equity Market. Current Economy Distribution / Channel management Good communication and presentation skills, Good interpersonal skills Ability to work with other people well, Willing to travel. Pro-activeness to know things and drive business and people How to Apply : EMAIL: cv to selvi.sai@upgrad.com / Whatsapp CV to 9361184170 (Or) Call me back to 9361184170 Thanks & Regards, Selvi Sai Chief Recruitment Specialist - Leadership & Mid / Senior Level Hiring m +91-9361184170 |

1. Hands on work on custom layout for analog blocks like High Speed SerDes and General purpose IO designs with Cadence Virtuoso on latest technologies like 5nm and below and also take leadership roles in delivery of IPs 2. Work on Floor planning, power design, signal routing strategy, EMIR awareness andparasitic optimisations 3. Understand and apply analog Layout techniques to ensure the design meets performance with minimum possible area and good yield. 4. Participate in building and enhancing layout flow for faster, higher quality design process. 5. Checking physical verifications like DRC/LVS/ERC/ANT/DFM and other IBM internal checks 6. Collaborate with Circuit Designers to solve challenging problems 7. Writing /PYTHON scripts to automate repetitive tasks 8. Work with Place and Route engineer to integrate custom macros into top level. 9. Able to perform design reviews across global team 10. Work closely with required global teams to ensure the success of the whole product. 11. Leadership in delivery of macros we plan to own from India Job requirements: 1. Experience in doing layouts for analog blocks like SerDes, ADCs, DACs, LDOs, PLLs, BGAP & amplifiers etc. 2. Experience in designing layouts for high-speed circuits is a plus. 3. Layout experience in the following technology nodes3nm, 5nm and 7nm FinFET. 4. Good team worker with multi-discipline, multi-cultural and multi-site environments 5. Strong fundamental knowledge in semiconductor device physics, layout principles, IC reliability and failure mechanisms 6. Good problem-solving skills are essential where problems are analysed upfront, identifying gaps, and providing optimum solutions7. Knowledge in Skill/perl/tcl/Python scripting is a plus. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise The Analog layout design engineer with experience in next generation Ultra high speed serial IO link (HSS) interface for Cognitive, ML,DL, and data center applications. The engineer needs to have knowledge in the design and development full custom analog layouts for ultra high speed 32G/50G/112G IO link interfaces. Preferred technical and professional experience Experience in 7 and 14 nm analog layout design. Working on Cutting edge technology and HSS domain . Quick learner, deep layout design knowledge, problem solving skills and good communication skills with cross teams across the Geos.

Location :- Vadodara / Kerela Post : Technical Surveyor Plant :- Service Provider Qualification :- Diploma/ BE Mechanical / Electrical /EC / IC Experience :- Fresher / Experience both can applicable Required Candidate profile Job Time :- 9am-6pm Salary :- 15,000 -20,000 CTC Facility :- No Post :- Surveyor ( 50% office work , 50 % site work ) Mo no : +91 90816 99700 / Mo No : 9081699500 / 9081699600