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Design and Verification Engineer

Design and Verification Engineer

Proxelera

4 - 9 years

10 - 20 Lacs

hyderabad bengaluru

Posted:3 days ago| Platform:

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Skills Required

design verification sv uvm gls soc design asic ddr amba verilog functional verification asic design rtl coding system verilog rtl design vlsi usb soc soc verification pcie verification vlsi design apb axi asic verification ethernet pci rtl verification ahb ip verification

Work Mode

Work from Office

Job Type

Full Time

Job Description

Design Verification Engineer

Key Responsibilities:

Develop and implement
verification plans, environments, and testbenches
using SystemVerilog/UVM.
Write and execute
test cases
for functional, regression, and coverage-driven verification.
Perform
debugging and root cause analysis
for design and verification issues.
Collaborate with RTL design, architecture, and validation teams to ensure quality deliverables.
Analyze
functional coverage metrics
and enhance test suites for improved quality.
Work on
assertion-based and formal verification techniques
where applicable.
Contribute to
automation and scripting
to streamline verification flows.

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