Senior PVD Process Engineer

About the Company:

Tata Electronics (a wholly owned subsidiary of Tata Sons Pvt. Ltd.) is building India’s first AI-enabled state-of-the-art Semiconductor Foundry. This facility will produce chips for applications such as power management IC, display drivers, microcontrollers (MCU) and high-performance computing logic, addressing the growing demand in markets such as automotive, computing and data storage, wireless communications and artificial intelligence.

Tata Electronics is a subsidiary of the Tata group. The Tata Group operates in more than 100 countries across six continents, with the mission 'To improve the quality of life of the communities we serve globally, through long term stakeholder value creation based on leadership with Trust.

About the role:

The Senior PVD Process Engineer is a technical leader responsible for developing, sustaining, and scaling advanced Physical Vapor Deposition processes for logic technology platforms. He/she owns critical thin-film steps across FEOL, MOL, and BEOL modules—ensuring stability, manufacturability, and yield for high-volume advanced-node production. This role requires deep understanding of metal deposition physics, interface engineering, logic-integration constraints, and the unique challenges associated with multi-patterned interconnects, contact resistance scaling, and device reliability. The engineer will drive module innovation, lead cross-functional problem-solving, mentor junior engineers, and support node migration for next-generation logic technologies.

Key Responsibilities

Process Ownership & Logic-Specific Innovation :

• Lead development and optimization of PVD processes supporting logic FEOL/MOL/BEOL modules (e.g., Ti/TiN, W/Ta/TaN, Cu seed, Ru, Co, Mo, Ni, selective metals, adhesion/barrier layers).
• Own and improve critical logic-related KPIs, including:

> Film resistivity, adhesion, and grain structure at scaled dimensions

> Contact resistance (Rc) and line resistance (Rline) for MOL/BEOL

> Pattern-dependent effects (AR, pinch-off, shading, overhang control)

> Stress engineering to avoid line collapse, wafer bow, and reliability failures

> Defectivity reduction for multi-patterning flows

• Drive introduction of new materials, high-ionization PVD (HiPIMS/IMP), selective deposition schemes, and novel barrierless/ultra-thin films for advanced logic interconnect scaling.
• Evaluate new chamber platforms, target materials, and hardware upgrades tailored for tight design rules and ultra-thin deposition requirements.

Cross-Functional Logic Integration Leadership

• Collaborate closely with logic integration, FEOL device, MOL contact, BEOL interconnect, CMP, and etch teams to ensure robust interface performance across modules.
• Lead structured problem-solving (RCA/8D/FMEA) for logic-specific issues such as:

> Via/trench fill failures

> Barrier/seed adhesion problems

> Contact resistivity excursions

> Gate stack metal adhesion and stress interactions

> BEOL electromigration and reliability escapes

• Support technology transfer, node migration, and early ramp activities for mature and next-generation logic nodes

Advanced Data & Process Control

• Utilize advanced analytics (SPC, FDC, ML-based drift detection, PCA, DOE, JMP/Minitab/Python) for process tuning, chamber stability, and wafer-to-wafer uniformity control.
• Build automated monitoring dashboards for:

> Chamber state prediction

> Target life modelling

> Anomaly detection in plasma/hardware signals

> OEE and throughput tracking

• Partner with APC/FDC teams to deploy model-based or real-time feedback control loops to prevent excursions in critical logic modules.

Mentorship & Knowledge Management

• Train junior engineers on experimental design, chamber matching, logic-specific process sensitivities, and high-volume manufacturing methodologies.
• Develop and maintain SOPs, BKMs, control plans, and safety procedures aligned with logic foundry standards.
• Present technical reviews and readiness updates to executives, customers, and cross-functional stakeholders.

Continuous Improvement & Cost Competitiveness

• Improve cycle time, chamber utilization, and target consumption through recipe tuning, PM optimization, and hardware reliability programs.
• Drive CoO improvements by optimizing target usage, improving uptime, and collaborating with global supply-chain teams for vendor benchmarking.
• Lead cross-fab harmonization for PVD process baselines, run rules, and excursion prevention protocols.

Qualifications

Education

• Master’s or Ph.D. in Materials Science, Chemical Engineering, Electrical Engineering, Physics, or related discipline.

Experience

• 5–12 years of process engineering experience in a logic foundry or advanced-node IDM environment.
• Proven ownership of PVD processes supporting logic FEOL, MOL, and BEOL modules (e.g., contact metallization, barrier/seed deposition, capping layers, or gate stack metals).
• Strong understanding of:
• Scaled interconnect and contact challenges (Rc reduction, electromigration, TDDB, gap-fill interactions)
• Ultra-thin metal deposition for advanced design rules (<10 nm)
• Interface engineering and adhesion mechanisms on dielectrics, high-k, and low-k materials
• Pattern loading, AR effects, and multi-patterning integration
• Proficiency with advanced metrology (XRR, XRD, SIMS, TEM/SEM, AFM, ellipsometry, CDSEM, 3D profilometry).
• Demonstrated ability to lead cross-functional teams, resolve high-impact excursions, and deliver stable high-volume processes.

Preferred Skills

• Experience with advanced PVD technologies such as HiPIMS, IMP, CVD-PVD hybrid platforms, self-ionized sputtering, or nucleation engineering for ultra-thin films.
• Familiarity with logic device architecture (Planar FET, FinFET, scaled BEOL stacks) and the corresponding metallization challenges.
• Strong documentation, presentation, and leadership skills.
• Experience coordinating work across multinational fabs or teams.