12 Electromigration Jobs

Hi All, Greetings from Eximietas Design...! We are hiring Senior Analog Layout Design Engineers/Leads. Experience: 4-12 years. Location: Hyderabad Job Description: ❖ Must understand techniques for managing IR drop, Electromigration, self-heating, RC delay and parasitic capacitance optimization. ❖ Understanding layout effects on the circuit such as speed and area. ❖ Ability to understand design constraints and implement high-quality layouts. ❖ Good communication skills and able to work with cross-functional teams. ❖ High level proficiency in C ADENCE/SYNOPSYS layout tools flow. ❖ Hands on experience on lower FINFET technology nodes. ❖ Scripting skills in PERL/SKILL are a plus. Interested Engineers please share your updated resume : maruthiprasad.e@eximietas.design Show more Show less

Requisition #: 15488 Our Mission: Powering Innovation That Drives Human Advancement When visionary companies need to know how their world-changing ideas will perform, they close the gap between design and reality with Ansys simulation. For more than 50 years, Ansys software has enabled innovators across industries to push boundaries by using the predictive power of simulation. From sustainable transportation to advanced semiconductors, from satellite systems to life-saving medical devices, the next great leaps in human advancement will be powered by Ansys. Innovate With Ansys, Power Your Career. Summary The Principal R&D Engineer leads the design and development of innovative solutions. In this role, the Principal R&D Engineer will act as a technical reference, working closely with customers, partners, application engineers and development teams to define and deploy major new flows, methods, and capabilities. Innovation in semiconductor design and manufacturing enables smaller device architectures with higher performance and energy efficiency for powering the smart product revolution. The physics associated with shrinking geometries, especially in the emerging 3-D IC, FinFET and stacked-die architectures, brings out design challenges related to power and reliability, affecting design closure. ANSYS simulation and modeling tools offer the sign-off accuracy and performance needed to ensure power noise integrity and reliability of even the most complex ICs, considering electromigration, thermal effects and electrostatic discharge phenomena. Responsibilities Leads the planning, architecture or research across multiple projects or disciplines Coordinates product design and development activities requiring extensive analysis in areas such as user experience, software design and solver research. Acts as a technical reference across groups or products Defines, develops, and employs best practices and maintains them through technical reviews and mentoring Performs highly complex bug verification, release testing, and beta support across multiple products. Coordinates the QA or product support teams on problems discovered and develops solutions Researches and understands the marketing requirements for products, including target environment, performance criteria and competitive issues. Works with strategic customers or proxies to assess needs and develop solutions Operates without direct supervision and functions as a high-level team leader, project manager, or software architect May be responsible for line management of a small technical team but primary duties are of an individual technical nature Minimum Qualifications BS in Engineering, Computer Science, or related field with 12 years’ experience, MS with 10 years’ experience Minimum three years of experience in EDA is must. Extensive commercial experience with enterprise software lifecycle and directing R&D projects Demonstrated leadership with a track record of delivering state-of-the-art results on complex problems Preferred Qualifications Experience in development of power integrity solutions. Demonstrated expertise in C/C++ & GPU programming, deep/machine learning algorithms Experience leading technical efforts to deliver innovative solutions that advance large-scale commercial products Proven ability to understand business requirements and translate them into software roadmaps and plans Ability to convey complex information in a clear way to stakeholders and development teams Ability to drive success across teams and geographies, and to mentor others At Ansys, we know that changing the world takes vision, skill, and each other. We fuel new ideas, build relationships, and help each other realize our greatest potential. We are ONE Ansys. We operate on three key components: our commitments to stakeholders, our values that guide how we work together, and our actions to deliver results. As ONE Ansys, we are powering innovation that drives human advancement Our Commitments Amaze with innovative products and solutions Make our customers incredibly successful Act with integrity Ensure employees thrive and shareholders prosper Our Values Adaptability: Be open, welcome what’s next Courage: Be courageous, move forward passionately Generosity: Be generous, share, listen, serve Authenticity: Be you, make us stronger Our Actions We commit to audacious goals We work seamlessly as a team We demonstrate mastery We deliver outstanding results VALUES IN ACTION Ansys is committed to powering the people who power human advancement. We believe in creating and nurturing a workplace that supports and welcomes people of all backgrounds; encouraging them to bring their talents and experience to a workplace where they are valued and can thrive. Our culture is grounded in our four core values of adaptability, courage, generosity, and authenticity. Through our behaviors and actions, these values foster higher team performance and greater innovation for our customers. We’re proud to offer programs, available to all employees, to further impact innovation and business outcomes, such as employee networks and learning communities that inform solutions for our globally minded customer base. Welcome What’s Next In Your Career At Ansys At Ansys, you will find yourself among the sharpest minds and most visionary leaders across the globe. Collectively, we strive to change the world with innovative technology and transformational solutions. With a prestigious reputation in working with well-known, world-class companies, standards at Ansys are high — met by those willing to rise to the occasion and meet those challenges head on. Our team is passionate about pushing the limits of world-class simulation technology, empowering our customers to turn their design concepts into successful, innovative products faster and at a lower cost. Ready to feel inspired? Check out some of our recent customer stories, here and here . At Ansys, it’s about the learning, the discovery, and the collaboration. It’s about the “what’s next” as much as the “mission accomplished.” And it’s about the melding of disciplined intellect with strategic direction and results that have, can, and do impact real people in real ways. All this is forged within a working environment built on respect, autonomy, and ethics. CREATING A PLACE WE’RE PROUD TO BE Ansys is an S&P 500 company and a member of the NASDAQ-100. We are proud to have been recognized for the following more recent awards, although our list goes on: Newsweek’s Most Loved Workplace globally and in the U.S., Gold Stevie Award Winner, America’s Most Responsible Companies, Fast Company World Changing Ideas, Great Place to Work Certified (China, Greece, France, India, Japan, Korea, Spain, Sweden, Taiwan, and U.K.). For more information, please visit us at www.ansys.com Ansys is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, and other protected characteristics. Ansys does not accept unsolicited referrals for vacancies, and any unsolicited referral will become the property of Ansys. Upon hire, no fee will be owed to the agency, person, or entity. Show more Show less

Looking for EMIR Engineer Job location- Pune. Exp.-5+yrs Prefer- Immediate joiner . Key Responsibilities: Perform IR drop and Electromigration (EM) analysis using tools like RedHawk, Voltus. Define EM/IR methodologies and flows. Collaborate with design teams to improve power grid design and robustness. Ensure sign-off quality results for high-performance SoCs. Create automated checks and regression flows. Required Skills: Strong knowledge of power integrity issues and reliability concerns at advanced nodes. Familiarity with power grid design, decap planning, and current estimation. Hands-on experience with EMIR tools (Ansys RedHawk, Cadence Voltus). Good knowledge of PnR flow and integration with IR/EM requirements. Regards, Sneha. Show more Show less

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description We are looking for technically sound and highly skilled High-speed SERDES IO PHY Layout designer with 12-15 years of experience. Apart from Serdes PHY Layout, the ideal candidate should have a strong background in analog/IO design principles, hands-on experience with layout tools, and a passion for solving challenging technical problems. Key Responsibilities: Develop and optimize Serdes PHY, analog and mixed-signal IC layouts, ensuring high performance and manufacturability. Collaborate with design engineers to understand design requirements and translate them into precise layouts. Strong experience in debugging DRC, ERC, LVS, EMIR and PERC issues independently. Work closely with the physical design team to integrate custom blocks into the overall chip design. Identify and resolve layout-related issues, providing creative solutions to meet design specifications. Conduct design reviews and provide technical feedback to improve layout practices and methodologies. Stay up-to-date with industry trends, tools, and technologies to continuously enhance layout processes. Qualifications 12-15 years of experience in Serdes Phy, Analog and Mixed-signal IC layout design. Proficiency in layout tools such as Cadence, Synopsys, or Mentor Graphics. Hands-on experience with custom layout design for various Serdes Phy, Analog and IO circuits is required, including expertise in Bandgap references, LDOs, Clocking circuits, GPIOs, DDR IOs. Familiarity with custom digital layout (i.e. high speed logic paths). Knowledge of signal integrity issues (i.e. clock/data routes, differential routing, shielding). Strong understanding of analog/IO design principles, including circuit performance and parasitic effects. Aware of layout techniques to mitigate ESD, latch-up issues. Holds advanced knowledge of CMOS and FinFET technologies and their impact on design and performance issues in deep sub-micron process nodes, specifically 5nm and below. Experience with layout concepts that incorporate reliability considerations, including techniques for managing electromigration (EM), IR drop, and self-heating. Experience with layout optimization for power, performance, and area (PPA) metrics. Excellent problem-solving skills and attention to detail. Effective communication and teamwork abilities. Preferred Skills: Knowledge of scripting languages (e.g., Skill,TCL and SVRF) for automation tasks. Qualifications Bachelor’s or Master’s degree in Electronics or Electrical Engineering Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at jobs.accommodations@sandisk.com to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying. Show more Show less

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Description Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day. Job Summary Cadence’s EAD flow provides incremental in-design analysis that includes parasitic extraction, electromigration (EM), and IR drop analysis. Looking for an individual with strong C++, data structures and EDA experience to join the Virtuoso Electrically Aware Design (EAD) R&D team. Qualifications BE/BTech/ME/MS/MTech in Electrical/Electronics Experience And Technical Skills Required Experience and Technical Skills required 2 years of software development experience, preferably in electronic circuits/EDA/layouts. Strong programming skills (C++, data structures) Experience in Qt will be a plus. Good understanding of an electronic circuit/parasitic/EM characteristics. We’re doing work that matters. Help us solve what others can’t. Show more Show less

Senior Analog Layout Engineer Exp : 5 to 8 years Work Location: Phoenix Aquila, Hyderabad, India Joining Timeline: Immediate to 15 Days preferred Maximum Notice Period: 30 Days (Strict) Job Description: Xeedo Technologies is seeking experienced Senior Analog Layout Engineers to work on-site for a global semiconductor leader – Micron Technology. The role involves end-to-end ownership of analog/custom layout blocks, physical verification, and collaboration with global design teams for successful project execution and tape-outs. Key Responsibilities: Design and development of analog and custom digital layout blocks in advanced CMOS technologies. Perform full physical verification using Mentor Graphics Calibre – including DRC, LVS, and Antenna checks. Ensure first-pass silicon success through high-quality layout practices and thorough verification. Interpret circuit schematics to create optimized layouts for power, area, performance, and reliability. Plan, estimate, and track layout tasks to meet project milestones and delivery schedules. Collaborate with cross-functional and global teams to resolve design and integration issues. Review work and mentor junior layout engineers when required. Required Skills: 5 to 8 years of hands-on experience in analog/custom layout design. Proficient in Cadence VLE/VXL layout tools. Strong experience with Mentor Graphics Calibre for DRC/LVS/Antenna verification. Hands-on layout experience in one or more of the following analog blocks: PLL, Bandgap, LDO, Temperature Sensors, ADC, DAC, Charge Pumps, Current Mirrors, Comparators, etc. Strong knowledge of layout principles such as: Matching, IR-drop, Electromigration, Parasitics, Latch-up, Crosstalk, and Coupling. Experience with multi-project environments and multiple successful tape-outs. Preferred Skills: Familiarity with custom memory layout methodologies. Experience in designing layout for: Bit cells, leaf cells, sense amps, decoders, and control logic. Educational Qualification: BE/BTech or ME/MTech in Electronics, Electrical, or VLSI Engineering. This is an exciting opportunity for engineers who are passionate about Analog Layout and eager to contribute to complex and cutting-edge semiconductor designs for a global client. Show more Show less

www.Sevyamultimedia.com Physical Design Manager / Senior Manager About Us We are a technology consulting company delivering best-in class Chip Design Services. Founded in 2008, we partner with top semiconductor companies in building a connected, safer tomorrow. With over 40+ tapeouts and expertise spanning the breadth of chip design, we offer a wide variety of Semiconductor skills SoC Design RTL Design, Integration, Lint/CDC/RDC, UPF IP/SoC UVM Verification PPA, Synthesis, Constraints Management Physical Design, Timing Closure, ECOs Sign-off - Timing, Power, EM/IR, DRC/LVS/ERC Approach We support a mix of engagement models to support diverse client requirements. Engagement Models Turnkey (SoW) Engagement Staff Augmentation (T&M) Offshore Design Center Key Enablers Hands on Leadership Proven Industry Experts TSMC DCA Parternship Collaboration with Academia ================ Physical Design Manager / Senior Manager #### **Job Summary:** We are seeking a highly experienced, hands-on and motivated Physical Design Manager/ Director to lead our physical design team. The ideal candidate will have extensive experience in block and top-level implementation, RDL/bump, pad location, EM/IR analysis, timing closure, physical verification closure, CAD flow bring-up, automation, planning, and estimation. This role involves managing complex design projects, leading a team of engineers, and ensuring the successful execution of physical design tasks from planning to tape-out. #### **Key Responsibilities:** - **Team Leadership:** - Lead, mentor, and manage a team of physical design engineers. - Foster a collaborative and innovative team environment. - Develop team skills through training and professional development initiatives. - **Project Management:** - Plan and estimate physical design tasks, resources, and schedules. - Track and report on project progress, ensuring timely delivery of milestones. - Coordinate with cross-functional teams, including design, verification, and packaging, to align physical design activities with project goals. - **Block and Top-Level Implementation:** - Perform and oversee block-level and top-level physical design implementation. - Ensure designs meet performance, power, area, and manufacturability requirements. - Perform detailed floorplanning, placement, and routing. - Constraints clean up, robustness of implementation - Timing feedback to design team and sign-off timing. - **RDL/Bump and Pad Location:** - Manage redistribution layer (RDL) and bump design for advanced packaging. - Optimize pad location for signal integrity and manufacturability. - **EM/IR Analysis and Timing Closure:** - Conduct electromigration (EM) and IR drop analysis to ensure robust power delivery. - Achieve timing closure through detailed static timing analysis (STA) and optimization. - **Physical Verification Closure:** - Perform physical verification (PV) closure, including design rule checking (DRC) and layout versus schematic (LVS). - Ensure designs comply with foundry and industry standards. - **CAD Flow and Automation:** - Develop and bring up CAD flows for physical design tasks. - Implement automation scripts to enhance efficiency and productivity. - **Continuous Improvement:** - Stay updated with the latest industry trends, tools, and methodologies in physical design. - Drive continuous improvement initiatives to enhance design processes and methodologies. - Implement best practices for physical design and contribute to the development of standards and processes. #### **Qualifications:** - **Education:** - Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. - **Experience:** - 10-15+ years of experience in physical design, with at least 3 years in a managerial or leadership role. - **Technical Skills:** - Extensive experience in block and top-level physical design implementation. - Proficiency in RDL/bump design and pad location optimization. - Strong knowledge of EM/IR analysis and timing closure techniques. - Experience with physical verification closure (DRC, LVS). - Familiarity with CAD flow development and automation. - **Soft Skills:** - Excellent leadership and team management abilities. - Strong problem-solving and analytical skills. - Effective communication and interpersonal skills. - Ability to work in a fast-paced, dynamic environment and manage multiple projects simultaneously. #### **Preferred Qualifications:** - Experience with advanced node technologies (e.g., FinFET, SOI). - Knowledge of scripting languages (e.g., Python, Perl) for automation. - Experience with EDA tools such as Cadence, Synopsys, or Mentor Graphics. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community" Show more Show less

Designing and developing high-performance flip flops, latches, multibit flip flops, voltage level shifters, power optimization cells, clock cells, and other complex circuits. Creating and refining environments for post-layout netlist extraction. Applying your expertise in CMOS device characteristics, design rules, latch-up, and electromigration to ensure robust designs. Optimizing digital circuits for better performance, power, and area (PPA). Performing statistical and variation analysis to enhance the reliability of designs. Collaborating with cross-functional teams to integrate designs into larger systems. The Impact You Will Have: Contributing to the creation of cutting-edge semiconductor technologies that power a wide range of applications. Enhancing the performance and efficiency of standard cell circuits, impacting the overall quality of our products. Driving innovation in power optimization and clock cell design, leading to more energy-efficient solutions. Improving the reliability and robustness of our designs through meticulous analysis and optimization. Collaborating on projects that shape the future of technology and influence industry standards. Leveraging your skills to solve complex engineering challenges, contributing to the success of Synopsys. What You ll Need: Experience in Standard Cell Circuit design of high-performance flip flops, latches, multibit flip flops, voltage level shifters, power optimization cells, and clock cells. Strong knowledge and hands-on experience in developing environments and extracting post-layout netlists. Good understanding of CMOS device characteristics, design rules, latch-up, and electromigration. Proficiency in digital circuit design and optimization for better PPA. Hands-on experience in statistical/variation analysis

Summary / Role Purpose The Lead R&D Engineer is responsible for the development of software products for semiconductor analysis. In this role, the Lead R&D Engineer will use advanced technical and problem-solving skills to help the team tackle complex issues, satisfy customer requirements, and accomplish development objectives. Innovation in semiconductor design and manufacturing enables smaller device architectures with higher performance and energy efficiency for powering the smart product revolution. The physics associated with shrinking geometries, especially in the emerging 3-D IC, FinFET and stacked-die architectures, brings out design challenges related to power and reliability, affecting design closure. ANSYS simulation and modeling tools offer the sign-off accuracy and performance needed to ensure power noise integrity and reliability of even the most complex ICs, considering electromigration, thermal effects and electrostatic discharge phenomena. The Lead R&D Engineer leads the design and development of software products and supporting systems. In this role, the Lead R&D Engineer will use expertise to develop strategic plans, refine requirements and provide technical leadership in achieving development objectives. Key Duties And Responsibilities Leads planning, architecture, or research at a project level. Employs best software practices and helps to maintain them through technical reviews and mentoring, also participating in planning and architecture. Performs complex software development activities that may require extensive analysis in areas including user experience, software design, solver research and implementations of new solver algorithms in C++ and Python. Develops and employs best practices and maintains them through technical reviews and mentoring. Performs complex bug verification, release testing and beta support across multiple products. Research problems discovered by QA or product support and develops solutions, collaborating with the QA/support team. Coordinates product design and development activities requiring extensive analysis in areas such as user experience, software design and solver research. Acts as a technical reference within a group or product. Operates without direct supervision and may function as a team leader, project manager, or software architect. May be responsible for line management of a small technical team but primary duties are of an individual technical nature. Minimum Education And Experience BTech in Engineering, Computer science, Physics, or related field with at least 6 years’ experience, MTech with 4 years’ experience Demonstrated experience with modern C++ and Agile development. Demonstrated experience with Python code development. Significant commercial experience with software design and development methodologies. Proven track record of crafting robust and efficient code. Preferred Qualifications And Skills Demonstrated experience with machine learning algorithms and techniques with GitHub code development Experience with software configuration management, data structures and algorithms Passion for crafting robust and efficient code Experience delivering high-quality products in a large-scale commercial software development environment Understanding of customer requirements and tools used in this domain Good communication and interpersonal skills Ability to work collaboratively in a geographically distributed team Show more Show less

Summary / Role Purpose This engineer will join as RD Engineer-II in the Research and Development team that creates state-of-the-art software for semiconductor analysis. Innovation in semiconductor design and manufacturing enables smaller device architectures with higher performance and energy efficiency for powering the smart product revolution. The physics associated with shrinking geometries, especially in the emerging 3-D IC, FinFET and stacked-die architectures, brings out design challenges related to power and reliability, affecting design closure. ANSYS simulation and modeling tools offer the sign-off accuracy and performance needed to ensure power noise integrity and reliability of even the most complex ICs, considering electromigration, thermal effects and electrostatic discharge phenomena. Key Duties And Responsibilities Performs development activities that may require extensive analysis in areas including user experience, software design and solver research. Employs best practices and helps to maintain them through technical reviews and mentoring Performs complex bug verification, release testing and beta support for assigned products. Researches problems discovered by QA or product support and develops solutions Anticipates future needs and technology evolution and proposes and participates in implementation of new solutions. Optimize code to improve tool run time and memory capacity. . . Minimum Education/Certification Requirements And Experience B.E./BTech. degree in Electronics Engineering, Computer Science or a related field like VLSI with 2 years of experience. Knowledge in C++ or Python Knowledge of the Linux operating system Strong background in data structures, algorithms, and debugging. Ability to learn quickly, understand complex systems and work closely with others. Preferred Qualifications And Skills Experience delivering high-quality products in a large-scale commercial software development environment. Good communication and interpersonal skills Experience with development, debugging and optimization of systems using distributed processing. Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned engineer with a passion for cutting-edge analog design. Your extensive experience with high-speed interfaces, particularly PCIe 6 and PCIe 7 or SerDes PHY designs, positions you as a technical leader in the field. You possess a deep understanding of transistor-level design and have a proven track record of successfully developing high-speed analog building blocks such as LDOs, Bandgap references, ADC/DAC, PLLs, and DLLs. Your expertise in CMOS technologies, including finFET and SOI processes, and your strong background in jitter budgeting analysis make you an invaluable asset to any team. You are adept at collaborating with cross-functional teams, mentoring junior engineers, and ensuring that designs meet stringent performance, power, and area targets. Your ability to oversee the porting of PHY designs to different technology nodes, while maintaining signal integrity and performance, demonstrates your versatility and commitment to excellence. What You’ll Be Doing: Lead the architecture and development of analog/mixed-signal blocks for PCIe 6 and PCIe 7 PHY designs. Ensure designs meet PCIe protocol standards, optimizing for performance, power, and area targets. Oversee the porting of PHY designs to different technology nodes, maintaining signal integrity and performance. Collaborate with cross-functional teams to integrate analog circuits into larger SerDes PHY systems. Develop and implement verification strategies for high-speed analog/mixed-signal circuits using advanced simulation tools. Supervise physical layout to minimize parasitics, device stress, and process variation impacts. Review simulation and measurement data for design validation and compliance with PCIe standards. Provide technical leadership and mentorship to junior engineers in analog/mixed-signal design best practices. Document design features, specifications, test plans, and methodologies for future reference. Collaborate with the characterization team to validate the electrical performance of circuits in silicon. The Impact You Will Have: Drive the development of next-generation PCIe 6 and PCIe 7 PHY designs, contributing to the advancement of high-speed interface technology. Ensure that Synopsys' analog/mixed-signal circuits meet stringent industry standards, enhancing the company's reputation for excellence. Facilitate the seamless integration of analog circuits into complex SerDes PHY systems, improving overall system performance. Mentor and develop junior engineers, fostering a culture of continuous learning and innovation within the team. Contribute to the successful porting of PHY designs across different technology nodes, ensuring versatility and adaptability. Enhance the company's design verification processes, leading to more robust and reliable high-speed analog/mixed-signal circuits. What You’ll Need: PhD with 5+ years, or MTech/MS with 10+ years of experience in analog/mixed-signal circuit design, with a focus on high-speed interfaces such as PCIe 6/7 or SerDes PHY designs. Extensive experience in transistor-level design of high-speed analog building blocks, such as LDOs, Bandgap references, ADC/DAC, PLLs, DLLs. Proven silicon experience in developing PHY circuits that meet strict PCIe standards. Expertise in high-speed SerDes AFE (Analog Front-End) development, including CTLE and CDR design. Experience designing high-speed SerDes transmitters, with in-depth knowledge of equalization techniques (e.g., DFE, FIR filters, TX pre-emphasis). Strong background in jitter budgeting analysis, including understanding the sources of jitter and strategies for minimizing its impact on signal integrity. Extensive experience with the porting of PHY designs across different technology nodes. Strong expertise in CMOS technologies, including finFET and SOI processes. In-depth understanding of the PCIe protocol, signal integrity requirements, jitter performance, and high-speed clocking. Proven ability to supervise layout design to minimize the effects of parasitics, process variations, and electromigration. Demonstrated ability to lead and mentor design teams, working across departments to ensure successful project outcomes. Who You Are: You are a collaborative and innovative problem solver with a keen eye for detail. Your strong communication skills enable you to effectively convey complex technical concepts to both technical and non-technical stakeholders. You are proactive, taking initiative to drive projects forward and overcome challenges. Your passion for continuous learning keeps you at the forefront of technological advancements, and your mentorship helps to cultivate a dynamic and skilled team. The Team You’ll Be A Part Of: You will join a highly skilled and dynamic team of engineers dedicated to pushing the boundaries of analog and mixed-signal design. Our team is focused on developing cutting-edge PCIe PHY designs, ensuring that they meet the highest standards of performance and reliability. Collaboration and innovation are at the core of our team's values, and we thrive on solving complex challenges together. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned professional with a minimum of 12 years of experience in analog and mixed signal circuit layout design, including at least 5 years of people management experience. You possess a deep understanding of electrical and electronic fundamentals, particularly in the context of FinFET nodes. Your expertise in EDA tools for custom mixed signal layout flows is unparalleled, and you have a proven track record of designing high-speed SERDES blocks. You are adept at troubleshooting physical verification issues and ensuring the delivery of high-quality, reliable silicon chips. Your leadership skills enable you to mentor and retain a diverse team of experienced layout designers, driving innovation and excellence in your projects. What You’ll Be Doing: Plan, estimate area/time, schedule, delegate tasks, and execute to meet project milestones in a multi-project environment. Communicate effectively with cross-functional teams for successful project execution. Create and review layout documents to ensure they meet quality standards and are delivered on time. Hire, mentor, and retain a mixed blend of experienced layout team members. Design and develop transistor to macro level analog and mixed signal layout, particularly for high-speed SERDES blocks. Perform device level floorplanning, placement, routing, and physical verification. Troubleshoot physical verification issues to achieve clean and desired results. The Impact You Will Have: Contribute to the design and development of high-performance silicon chips. Ensure the reliability and functionality of analog and mixed signal layouts. Drive innovation by applying advanced knowledge of semiconductor technologies. Enhance the quality and efficiency of layout design processes. Support the successful delivery of projects within tight deadlines. Collaborate with multidisciplinary teams to achieve organizational goals. What You’ll Need: Minimum 12 years of experience in analog and mixed signal circuit layout, including at least 5 years of people management experience. Hands-on experience in complete analog layout flow from floorplanning and device placement to GDS release. Strong knowledge of electrical and electronic fundamentals, especially in FinFET node technologies. Proficiency in EDA tools for custom mixed signal layout flows. - In-depth knowledge of FinFET rules, constraints, and techniques to mitigate parasitic effects. Strong understanding of electromigration, ESD, and LUP fundamentals, with skills in analyzing EMIR, ESD PERC, and ESD CNOD results. Experience in product release flow and quality checks. Who You Are: A proactive leader with excellent communication and mentoring skills. Detail-oriented and committed to delivering high-quality results. Innovative and capable of driving technological advancements. Collaborative and able to work effectively with cross-functional teams. A problem-solver with strong analytical skills. The Team You’ll Be A Part Of: You will be part of a dynamic and innovative layout design team focused on creating high-performance analog and mixed signal layouts. The team is dedicated to excellence and continuous improvement, working collaboratively to achieve the organization's goals. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less