34 Electromigration Jobs

Greetings from Eximietas Design! We are actively looking to hire Senior Analog Layout Leads/Architects with 7-15 years of experience in lower FINFET technology nodes, preferably TSMC 5nm, to join our growing team in Hyderabad. We prefer candidates with a notice period of 30 days or less. As a Senior Analog Layout Lead/Architect, you will be responsible for contributing to cutting-edge analog layout design. You should have expertise in IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization. A solid understanding of how layout impacts circuit performance, such as speed and area, is essential. You should be able to implement layouts that meet tight design constraints while delivering high quality results. Hands-on experience with CADENCE/SYNOPSYS layout tools and flows is required, and familiarity with scripting languages like PERL/SKILL is a plus. Strong communication skills are necessary as you will be working with cross-functional teams. If you are interested in this opportunity or know someone who would be suitable, please send your updated resume to maruthiprasad.e@eximietas.design. Referrals are highly appreciated. We look forward to connecting with talented engineers who are passionate about pushing the boundaries of analog layout design! Maruthhi Naidu Talent Associate - VLSI Manager Eximietas Design - Visakhapatnam maruthiprasad.e@eximietas.design +91 8088969910.,

Hi...! Greetings from Eximietas Design...! We are actively looking to hire Senior Analog Layout Leads/Architects with (TSMC 5nm / TSMC 7nm preferred) 7–15 years of experience to join our growing team. 📍 Locations: Visakhapatnam (Vizag). 📅 Notice Period: 30 days or less preferred. Job Description: We’re seeking highly skilled professionals with a strong background in lower FINFET technology nodes (TSMC 5nm/7nm preferred) to contribute to cutting-edge analog layout design. Key Skills & Requirements: Expertise in IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization. Solid understanding of how layout impacts circuit performance (speed, area, etc.). Ability to implement layouts that meet tight design constraints and deliver high quality. Hands-on experience with CADENCE/SYNOPSYS layout tools and flows. Familiarity with scripting languages (PERL/SKILL) is a plus. Strong communication skills and experience working with cross-functional teams. If this opportunity interests you—or if you know someone suitable—please send your updated resume to: 📧 maruthiprasad.e@eximietas.design. Referrals are highly appreciated. We look forward to connecting with talented engineers passionate about pushing the boundaries of analog layout design! Maruthhi Naidu Talent Associate - VLSI Manager Eximietas Design - Visakhapatnam maruthiprasad.e@eximietas.design +91 8088969910.

Hi...! Greetings from Eximietas Design...! We are actively looking to hire Senior Analog Layout Design Engineers / Leads with (TSMC 5nm / TSMC 7nm preferred) 7–15 years of experience to join our growing team. 📍 Locations: Visakhapatnam (Vizag) 📅 Notice Period: 30 days or less preferred. Job Description: We’re seeking highly skilled professionals with a strong background in lower FINFET technology nodes (TSMC 5nm/7nm preferred) to contribute to cutting-edge analog layout design. Key Skills & Requirements: Expertise in IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization. Solid understanding of how layout impacts circuit performance (speed, area, etc.). Ability to implement layouts that meet tight design constraints and deliver high quality. Hands-on experience with CADENCE/SYNOPSYS layout tools and flows. Familiarity with scripting languages (PERL/SKILL) is a plus. Strong communication skills and experience working with cross-functional teams. If this opportunity interests you—or if you know someone suitable—please send your updated resume to: 📧 maruthiprasad.e@eximietas.design. Referrals are highly appreciated. We look forward to connecting with talented engineers passionate about pushing the boundaries of analog layout design! Maruthhi Naidu Talent Associate - VLSI Manager Eximietas Design - Visakhapatnam maruthiprasad.e@eximietas.design +91 8088969910.

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a dedicated and innovative engineer with a solid background in Standard Cell Circuit design, particularly focusing on high-performance flip flops, latches, multibit flip flops, voltage level shifters, power optimization cells, clock cells, and other complex circuits. Your deep understanding of CMOS device characteristics, design rules, latch-up, and electromigration sets you apart. With 2-4 years of relevant experience, you have honed your skills in developing environments and extracting post-layout netlists. Your proficiency in digital circuit design and optimization for better PPA is commendable. Additionally, statistical/variation analysis is within your expertise. A decent knowledge of Python/Shell/ICV coding is preferable, and having a good understanding of standard cell layout is a plus. You excel in both verbal and written communication, making you an ideal candidate for this role. What You’ll Be Doing: Designing and developing high-performance flip flops, latches, multibit flip flops, voltage level shifters, power optimization cells, clock cells, and other complex circuits. Creating and refining environments for post-layout netlist extraction. Applying your expertise in CMOS device characteristics, design rules, latch-up, and electromigration to ensure robust designs. Optimizing digital circuits for better performance, power, and area (PPA). Performing statistical and variation analysis to enhance the reliability of designs. Collaborating with cross-functional teams to integrate designs into larger systems. The Impact You Will Have: Contributing to the creation of cutting-edge semiconductor technologies that power a wide range of applications. Enhancing the performance and efficiency of standard cell circuits, impacting the overall quality of our products. Driving innovation in power optimization and clock cell design, leading to more energy-efficient solutions. Improving the reliability and robustness of our designs through meticulous analysis and optimization. Collaborating on projects that shape the future of technology and influence industry standards. Leveraging your skills to solve complex engineering challenges, contributing to the success of Synopsys. What You’ll Need: Experience in Standard Cell Circuit design of high-performance flip flops, latches, multibit flip flops, voltage level shifters, power optimization cells, and clock cells. Strong knowledge and hands-on experience in developing environments and extracting post-layout netlists. Good understanding of CMOS device characteristics, design rules, latch-up, and electromigration. Proficiency in digital circuit design and optimization for better PPA. Hands-on experience in statistical/variation analysis. Who You Are: You are a detail-oriented and analytical thinker with a passion for circuit design and optimization. Your ability to collaborate effectively with cross-functional teams and communicate technical concepts clearly is essential. You are a problem solver who enjoys tackling complex engineering challenges and continuously seeks to improve and innovate. Your strong technical background and hands-on experience make you a valuable asset to any team. The Team You’ll Be A Part Of: You will be part of a dynamic and innovative engineering team dedicated to pushing the boundaries of semiconductor technology. Our team focuses on designing and developing advanced standard cell circuits, collaborating closely with other engineering disciplines to create integrated solutions that meet the highest performance and reliability standards. Together, we drive the technological advancements that shape the future of the industry. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Greetings from Eximietas Design! We are actively seeking Senior Analog Layout Design Engineers / Leads with a minimum of 5-12 years of experience in the field, preferably with expertise in TSMC 5nm or TSMC 7nm technology nodes. Join our dynamic team at locations in Bengaluru, Vizag, or Hyderabad. As a Senior Analog Layout Design Engineer, you will be responsible for contributing to cutting-edge analog layout design, focusing on aspects such as IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization. Your role will involve implementing layouts that adhere to strict design constraints while ensuring high quality and optimal circuit performance. Key Skills & Requirements: - Proficiency in IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization. - Strong comprehension of how layout impacts circuit performance metrics such as speed and area. - Ability to create layouts that meet rigorous design constraints and uphold quality standards. - Hands-on experience with CADENCE/SYNOPSYS layout tools and workflows. - Familiarity with scripting languages such as PERL/SKILL is considered a plus. - Excellent communication skills with a proven track record of collaborating effectively with cross-functional teams. If this opportunity aligns with your expertise and interests, or if you know someone who would be a suitable fit, please forward your updated resume to maruthiprasad.e@eximietas.design. Referrals are highly appreciated. We are excited to connect with talented engineers who are passionate about pushing the boundaries of analog layout design! Best regards, Maruthhi Naidu Talent Associate - VLSI Manager Eximietas Design - Visakhapatnam Email: maruthiprasad.e@eximietas.design Phone: +91 8088969910,

Hi Greetings from Eximietas Design! We are actively looking to hire Senior Analog Layout Design Engineers / Leads with 7–15 years of experience to join our growing team. 📍 Locations: Bangalore, Hyderabad & Visakhapatnam. 📅 Notice Period: 30 days or less preferred. Job Description: We’re seeking highly skilled professionals with a strong background in lower FINFET technology nodes (TSMC 5nm preferred) to contribute to cutting-edge analog layout design. Key Skills & Requirements: Expertise in IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization. Solid understanding of how layout impacts circuit performance (speed, area, etc.). Ability to implement layouts that meet tight design constraints and deliver high quality. Hands-on experience with CADENCE/SYNOPSYS layout tools and flows. Familiarity with scripting languages (PERL/SKILL) is a plus. Strong communication skills and experience working with cross-functional teams. If this opportunity interests you—or if you know someone suitable—please send your updated resume to: 📧 maruthiprasad.e@eximietas.design. Referrals are highly appreciated. We look forward to connecting with talented engineers passionate about pushing the boundaries of analog layout design! Maruthhi Naidu Talent Associate - VLSI Manager Eximietas Design - Visakhapatnam maruthiprasad.e@eximietas.design +91 8088969910.

Hi Greetings from Eximietas Design! We are actively looking to hire Senior Analog Layout Design Engineers / Leads with 7–15 years of experience to join our growing team. 📍 Locations: Bangalore, Hyderabad & Visakhapatnam. 📅 Notice Period: 30 days or less preferred. Job Description: We’re seeking highly skilled professionals with a strong background in lower FINFET technology nodes (TSMC 5nm/TSMC 7nm preferred) to contribute to cutting-edge analog layout design. Key Skills & Requirements: Expertise in IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization. Solid understanding of how layout impacts circuit performance (speed, area, etc.). Ability to implement layouts that meet tight design constraints and deliver high quality. Hands-on experience with CADENCE/SYNOPSYS layout tools and flows. Familiarity with scripting languages (PERL/SKILL) is a plus. Strong communication skills and experience working with cross-functional teams. If this opportunity interests you—or if you know someone suitable—please send your updated resume to: 📧 maruthiprasad.e@eximietas.design. Referrals are highly appreciated. We look forward to connecting with talented engineers passionate about pushing the boundaries of analog layout design! Maruthhi Naidu Talent Associate - VLSI Manager Eximietas Design - Visakhapatnam maruthiprasad.e@eximietas.design +91 8088969910.

Hi Greetings from Eximietas Design! We are actively looking to hire Senior Analog Layout Design Engineers / Leads with (TSMC 5nm / TSMC 7nm preferred) 7–15 years of experience to join our growing team. 📍 Locations: Vizag/Bengaluru/Hyd 📅 Notice Period: 30 days or less preferred. Job Description: We’re seeking highly skilled professionals with a strong background in lower FINFET technology nodes (TSMC 5nm/7nm preferred) to contribute to cutting-edge analog layout design. Key Skills & Requirements: Expertise in IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization. Solid understanding of how layout impacts circuit performance (speed, area, etc.). Ability to implement layouts that meet tight design constraints and deliver high quality. Hands-on experience with CADENCE/SYNOPSYS layout tools and flows. Familiarity with scripting languages (PERL/SKILL) is a plus. Strong communication skills and experience working with cross-functional teams. If this opportunity interests you—or if you know someone suitable—please send your updated resume to: 📧 maruthiprasad.e@eximietas.design. Referrals are highly appreciated. We look forward to connecting with talented engineers passionate about pushing the boundaries of analog layout design! Maruthhi Naidu Talent Associate - VLSI Manager Eximietas Design - Visakhapatnam maruthiprasad.e@eximietas.design +91 8088969910.

Hi Greetings from Eximietas Design! We are actively looking to hire Senior Analog Layout Design Engineers / Leads with (TSMC 5nm / TSMC 7nm preferred) 7–15 years of experience to join our growing team. 📍 Locations: Vizag/Bengaluru/Hyd 📅 Notice Period: 30 days or less preferred. Job Description: We’re seeking highly skilled professionals with a strong background in lower FINFET technology nodes (TSMC 5nm/7nm preferred) to contribute to cutting-edge analog layout design. Key Skills & Requirements: Expertise in IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization. Solid understanding of how layout impacts circuit performance (speed, area, etc.). Ability to implement layouts that meet tight design constraints and deliver high quality. Hands-on experience with CADENCE/SYNOPSYS layout tools and flows. Familiarity with scripting languages (PERL/SKILL) is a plus. Strong communication skills and experience working with cross-functional teams. If this opportunity interests you—or if you know someone suitable—please send your updated resume to: 📧 maruthiprasad.e@eximietas.design. Referrals are highly appreciated. We look forward to connecting with talented engineers passionate about pushing the boundaries of analog layout design! Maruthhi Naidu Talent Associate - VLSI Manager Eximietas Design - Visakhapatnam maruthiprasad.e@eximietas.design +91 8088969910.

Hi....! Greetings from Eximietas Design! We are actively looking to hire Senior Analog Layout Design Engineers / Leads with (TSMC 5nm/TSMC 7nm preferred) 5–12 years of experience to join our growing team. 📍 Locations: Bengaluru/Vizag/Hyd. 📅 Notice Period: Immediate - 15 days Preferred Job Description: We’re seeking highly skilled professionals with a strong background in lower FINFET technology nodes (TSMC 5nm/7nm preferred) to contribute to cutting-edge analog layout design. Key Skills & Requirements: Expertise in IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization. Solid understanding of how layout impacts circuit performance (speed, area, etc.). Ability to implement layouts that meet tight design constraints and deliver high quality. Hands-on experience with CADENCE/SYNOPSYS layout tools and flows. Familiarity with scripting languages (PERL/SKILL) is a plus. Strong communication skills and experience working with cross-functional teams. If this opportunity interests you—or if you know someone suitable—please send your updated resume to: 📧 maruthiprasad.e@eximietas.design. Referrals are highly appreciated. We look forward to connecting with talented engineers passionate about pushing the boundaries of analog layout design! Maruthhi Naidu Talent Associate - VLSI Manager Eximietas Design - Visakhapatnam maruthiprasad.e@eximietas.design +91 8088969910.

As a candidate for this position, you should hold a Bachelor's degree in Computer Science, IT, a related field, or possess equivalent practical experience. Additionally, you should have at least 5 years of experience in static timing analysis, synthesis, physical design, and automation. It is crucial that you have expertise in physical design tool automation, including synthesis, P&R, and sign-off tools. In addition to the minimum qualifications, preferred qualifications for this role include experience in extracting design parameters, Quality of Results metrics, and analyzing data trends. You should also have knowledge of timing constraints, convergence, and signoff processes, as well as familiarity with parasitic extraction tools and flow. Proficiency in Register-Transfer Level (RTL) languages such as Verilog/SystemVerilog is required, along with a strong understanding of Static Timing Analysis (STA), Electromigration and IR Drop (EMIR), and PDV signoff methodologies. Join a dynamic team that is dedicated to pushing boundaries and developing custom silicon solutions that drive the future of Google's direct-to-consumer products. Your contributions will play a key role in innovating products that are beloved by millions worldwide. By leveraging your expertise, you will help shape the next generation of hardware experiences that deliver unparalleled performance, efficiency, and integration. In this role, your responsibilities will include driving sign-off timing methodologies for mobile System on a chip (SoCs) to optimize Power Performance Area (PPA) and yield. You will analyze power performance area trade-offs across various methodologies and technologies, as well as work on prototyping subsystems to deliver optimized PPA recipes. Collaboration with cross-functional teams including architecture, Internet Protocols (IPs), design, power, and sign-off methodology is essential. Furthermore, you will engage with foundry partners to enhance signoff methodology for improved convergence and yield.,

You will be responsible for the layout of Analog and mixed-signal modules in CMOS and Power Technologies, with a specific focus on DC-DC converters for power management ICs. This includes designing Analog and mixed-signal system resource blocks such as POR, Bandgap, LDO, Oscillator, amplifier, and power FET. You will also be involved in chip floor-planning, pad ring layout, power busing, bonding, and tape-out activities. Your role will require a deep understanding of layout verification processes like DRC, LVS, Latch-up, and Electro-migration. Additionally, you will collaborate closely with designers to define block layout requirements, match patterns, and ensure signal integrity. To qualify for this position, you should hold a Diploma, Bachelor's, or Master's Degree in Electrical/Electronic Engineering, Physics, or a related field with 7 to 10 years of relevant experience. Your expertise should include Analog and mixed-signal layout, especially in CMOS and Power Technologies. Strong analytical skills and a comprehensive understanding of Analog Layout are essential for this role. Familiarity with power switch layout, electro-migration, and thermal analysis would be advantageous. Proficiency in computer-aided design tools and methodologies is also required to excel in this position.,

Greetings from Eximietas Design! We are actively seeking Senior Analog Layout Design Engineers / Leads with 7-15 years of experience to join our expanding team in Bangalore, Hyderabad, and Visakhapatnam. The ideal candidate should have a strong background in lower FINFET technology nodes, particularly TSMC 5nm, to contribute to cutting-edge analog layout design. As a Senior Analog Layout Design Engineer / Lead, you will be responsible for optimizing IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance in layouts. You should have a solid understanding of how layout impacts circuit performance, such as speed and area, and the ability to implement high-quality layouts that meet tight design constraints. Key Skills & Requirements: - Expertise in IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization. - Solid understanding of how layout impacts circuit performance. - Ability to implement layouts meeting tight design constraints and delivering high quality. - Hands-on experience with CADENCE/SYNOPSYS layout tools and flows. - Familiarity with scripting languages (PERL/SKILL) is a plus. - Strong communication skills and experience collaborating with cross-functional teams. If you find this opportunity intriguing or know someone who would be a good fit, please send your updated resume to maruthiprasad.e@eximietas.design. Referrals are highly appreciated. We are excited to connect with talented engineers who are passionate about pushing the boundaries of analog layout design! Maruthhi Naidu Talent Associate - VLSI Manager Eximietas Design - Visakhapatnam Contact: +91 8088969910.,

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and highly skilled engineer committed to advancing the field of high-speed analog design. You bring a wealth of experience in designing critical analog and mixed-signal blocks, particularly for cutting-edge PCIe 6 and PCIe 7 or SerDes PHY solutions. Your technical expertise encompasses transistor-level design, deep knowledge of CMOS (including finFET and SOI processes), and a proven ability to create robust high-speed building blocks—such as LDOs, Bandgap references, ADC/DACs, PLLs, and DLLs—that consistently meet rigorous performance, power, and area targets. You thrive in collaborative, multidisciplinary environments, where your clear communication and mentoring skills empower both peers and junior engineers to excel. Your proactive approach to problem-solving and your dedication to continuous improvement ensure that you stay at the forefront of technology trends. You are adept at analyzing and mitigating jitter, maintaining signal integrity, and ensuring compliance with demanding industry standards. Your experience with porting PHY designs across technology nodes demonstrates your adaptability and commitment to delivering high-quality, innovative solutions. You value documentation, knowledge sharing, and actively contribute to a culture of learning and technical excellence. Most importantly, you are excited to join a team that values diversity, encourages bold ideas, and is committed to shaping the future of high-speed connectivity. You see challenges as opportunities and bring a growth mindset to every project you undertake. What You’ll Be Doing: Designing and developing advanced analog/mixed-signal blocks for PCIe 6 and PCIe 7 PHY architectures under the guidance of senior technical leaders. Ensuring that all designs strictly adhere to PCIe protocol standards, optimizing for performance, power, and area efficiency. Porting high-speed PHY designs to various technology nodes while maintaining signal integrity and maximizing performance. Collaborating with cross-functional teams—including digital, verification, and layout groups—to successfully integrate analog circuits into complex SerDes PHY systems. Implementing innovative verification strategies for high-speed analog/mixed-signal circuits using state-of-the-art simulation and modeling tools. Working closely with layout teams to minimize parasitics, device stress, and process variation impacts on overall circuit performance. Analyzing simulation and silicon measurement data to validate designs and ensure compliance with PCIe standards. Mentoring junior engineers and promoting best practices in analog/mixed-signal design and verification. Documenting design features, specifications, and test methodologies for future reference and team knowledge sharing. Partnering with characterization teams to validate electrical performance of circuits in silicon and resolve technical challenges. The Impact You Will Have: Drive the development of next-generation PCIe 6 and PCIe 7 PHY designs, advancing high-speed interface technologies that power tomorrow’s data-driven world. Ensure Synopsys’ analog/mixed-signal circuits exceed industry standards, reinforcing our reputation for technical excellence and innovation. Facilitate seamless integration of analog circuits into sophisticated SerDes PHY systems, enhancing overall performance and reliability. Mentor and develop junior engineers, fostering a collaborative and innovative team environment. Lead successful porting of PHY designs across multiple technology nodes, delivering versatile and scalable solutions for diverse customer needs. Strengthen verification and validation processes, resulting in robust, reliable, and high-performing analog/mixed-signal circuits. What You’ll Need: PhD with 3+ years, or MTech/MS with 7+ years of experience in analog/mixed-signal circuit design focused on high-speed interfaces such as PCIe 6/7 or SerDes PHY designs. Proven expertise in transistor-level design of high-speed analog building blocks (e.g., LDOs, Bandgap references, ADC/DACs, PLLs, DLLs). Demonstrated silicon experience in developing PHY circuits compliant with PCIe standards. Strong background in high-speed SerDes AFE development, including CTLE and CDR design. Experience designing high-speed SerDes transmitters and deep knowledge of equalization techniques (e.g., DFE, FIR filters, TX pre-emphasis). Solid foundation in jitter budgeting analysis and expertise in minimizing jitter impact on signal integrity. Experience porting PHY designs across different technology nodes and deep knowledge of CMOS, finFET, and gate-all-around processes. Comprehensive understanding of the PCIe protocol, signal integrity, jitter performance, and high-speed clocking. Ability to collaborate with layout teams to minimize parasitics, process variations, and electromigration effects. Proven track record of effective teamwork and successful project outcomes across multidisciplinary teams. Who You Are: Innovative thinker with a passion for high-speed analog design and technology advancement. Collaborative team player who values diversity and inclusion. Effective communicator, able to translate complex technical concepts to a variety of audiences. Mentor and coach, eager to support the development of junior engineers. Detail-oriented problem solver with a commitment to quality and continuous improvement. Adaptable and resourceful, thriving in fast-paced, changing environments. The Team You’ll Be A Part Of: You will join a world-class analog/mixed-signal design team at Synopsys, focused on developing high-speed interface IP for next-generation semiconductor products. The team is composed of passionate engineers from diverse backgrounds, collaborating closely to deliver innovative solutions that drive the future of connectivity. Our culture emphasizes technical excellence, knowledge sharing, and continuous learning, providing an environment where your skills and ideas are valued and your career can thrive. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Greetings from Eximietas Design! We are actively seeking to hire Senior Analog Layout Design Engineers / Leads with 7-15 years of experience in lower FINFET technology nodes, preferably TSMC 5nm, to join our team in Bangalore, Hyderabad, or Visakhapatnam. A notice period of 30 days or less is preferred for this position. As a Senior Analog Layout Design Engineer/Lead at Eximietas Design, you will be responsible for contributing to cutting-edge analog layout design. Your expertise in IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization will be essential. You should have a solid understanding of how layout impacts circuit performance, such as speed and area, and the ability to implement layouts that meet tight design constraints while delivering high quality results. Hands-on experience with CADENCE/SYNOPSYS layout tools and flows is required, and familiarity with scripting languages (PERL/SKILL) is a plus. Strong communication skills and experience collaborating with cross-functional teams are also key to success in this role. If you are interested in this opportunity or know someone suitable, please send your updated resume to maruthiprasad.e@eximietas.design. Referrals are highly appreciated. We are looking forward to connecting with talented engineers who are passionate about pushing the boundaries of analog layout design. Maruthhi Naidu Talent Associate - VLSI Manager Eximietas Design - Visakhapatnam maruthiprasad.e@eximietas.design +91 8088969910.,

Job Description We are seeking a talented and detail-oriented Physical Backend Design Engineer to join our IC (Integrated circuit) development team. The role involves key aspects of physical design, including automated place and route, floorplanning, clock tree synthesis (CTS), static timing analysis (STA), power analysis, and physical verification (DRC/LVS). The ideal candidate will have a strong knowledge of physical design methodologies, experience with industry-standard tools, and a passion for delivering high-quality semiconductor solutions. How You Will Contribute And What You Will Learn Perform floorplanning, partitioning, and optimization to achieve area, power, and performance targets. Execute automated place and route (PnR) using industry-standard tools to generate physical layouts. Implement clock tree synthesis (CTS), ensuring low skew and efficient clock distribution. Conduct static timing analysis (STA) to verify timing closure and ensure the design meets performance requirements. Perform power analysis, including IR drop and electromigration (EM) checks, to optimize power distribution networks. Conduct physical verification tasks, including design rule checks (DRC) and layout vs. schematic (LVS) checks, to ensure manufacturability and compliance with foundry standards. Collaborate with design, verification, and DFT teams to resolve physical design challenges and improve chip performance. Work closely with foundry teams to address process technology issues and implement best practices. Key Skills And Experience You have: Bachelor’s Degree in Electrical Engineering, Computer Engineering, or a related field (Master’s preferred) 3+ years of experience in physical backend design for ICs. Complex chip designs through all stages of physical implementation Experience with tape-out of designs for advanced nodes is highly desirable Strong knowledge of physical design concepts, including place and route (PnR), clock tree synthesis (CTS), static timing analysis (STA) and power grid design Experience with physical verification tools like Cadence Pegasus or Mentor Calibre Familiarity with parasitic extraction tools (e.g., StarRC, Quantus, Calibre xRC) Scripting skills in Python, Tcl, Perl, or Shell for automation Required Tools: Cadence Innovus, Cadence Quantus, Cadence Tempus, Cadence Pegasus suite It would be nice if you also had: Experience with advanced process nodes (e.g., 7nm and below) Knowledge of low-power design techniques, such as multi-Vt, multi-Vdd, or clock gating Familiarity with DFT concepts and tools, Chip packaging and thermal analysis considerations, FinFET technology and 3D IC design methodologies About Us Come create the technology that helps the world act together Nokia is committed to innovation and technology leadership across mobile, fixed and cloud networks. Your career here will have a positive impact on people’s lives and will help us build the capabilities needed for a more productive, sustainable, and inclusive world. We challenge ourselves to create an inclusive way of working where we are open to new ideas, empowered to take risks and fearless to bring our authentic selves to work What we offer Nokia offers continuous learning opportunities, well-being programs to support you mentally and physically, opportunities to join and get supported by employee resource groups, mentoring programs and highly diverse teams with an inclusive culture where people thrive and are empowered. Nokia is committed to inclusion and is an equal opportunity employer Nokia has received the following recognitions for its commitment to inclusion & equality: One of the World’s Most Ethical Companies by Ethisphere Gender-Equality Index by Bloomberg Workplace Pride Global Benchmark At Nokia, we act inclusively and respect the uniqueness of people. Nokia’s employment decisions are made regardless of race, color, national or ethnic origin, religion, gender, sexual orientation, gender identity or expression, age, marital status, disability, protected veteran status or other characteristics protected by law. We are committed to a culture of inclusion built upon our core value of respect. Join us and be part of a company where you will feel included and empowered to succeed. About The Team Nokia Bell Labs is the world-renowned research arm of Nokia, having invented many of the foundational technologies that underpin information and communications networks and all digital devices and systems. This research has produced nine Nobel Prizes, five Turing Awards and numerous other awards.

You are invited to join Eximietas Design as a Senior Analog Layout Design Engineer/Lead with 7-15 years of experience. We are a rapidly growing team seeking professionals skilled in lower FINFET technology nodes, particularly TSMC 5nm. Your role will involve working on cutting-edge analog layout design projects. Your key responsibilities will include expertise in IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization. A solid understanding of how layout impacts circuit performance, such as speed and area, is essential. You must be able to implement layouts that meet strict design constraints while ensuring high quality. Proficiency in CADENCE/SYNOPSYS layout tools and flows is required, and familiarity with scripting languages like PERL/SKILL would be advantageous. Strong communication skills are necessary as you will collaborate with cross-functional teams. If you are interested in this exciting opportunity or know someone who might be a suitable fit, please send your updated resume to maruthiprasad.e@eximietas.design. Referrals are highly appreciated, and we are eager to connect with talented engineers who are passionate about pushing the boundaries of analog layout design. We look forward to welcoming you to our dynamic team at Eximietas Design.,

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Job Description Key Responsibilities Lead EM/IR analysis and closure efforts at SoC/top-level, focusing on power grid robustness, EM reliability, and IR drop minimization across complex multi-block subsystems. Architect and evolve EM/IR methodologies and PNR strategies tailored for top-level power nets, integrating thermal-aware and hierarchical analysis techniques. Drive automation and development of EM/IR signoff flows, including integration with parasitic extraction, thermal maps, and advanced simulation tools. Provide technical leadership and mentorship to engineering teams, promoting best practices in EM/IR analysis, PNR integration, and power integrity closure. Collaborate cross-functionally with physical design, timing, and verification teams to resolve EM/IR-related design challenges and optimize power delivery network performance. Communicate complex technical findings clearly to senior management and customers, influencing design and reliability decisions at the SoC level. Qualifications 10+ years of experience specializing in Electromigration (EM) and IR drop analysis at SoC or top-level chip hierarchy, combined with strong Place and Route (PNR) background at advanced nodes (7nm, 5nm, or below). Proven expertise in full-chip and hierarchical EM/IR signoff flows, including power grid design, EM/IR-aware routing, and reliability analysis at SoC/top-level. Hands-on experience with industry-leading EM/IR and PNR tools such as Synopsys RedHawk, Cadence Voltus, Ansys PrimeX, Synopsys ICC2, Innovus, and PrimeTime. Strong scripting and automation skills (Tcl, Perl, Python) for developing and optimizing EM/IR and PNR flows at the top-level hierarchy. Deep understanding of SoC power delivery networks (PDN), EM/IR failure mechanisms, and thermal effects including Joule heating and thermomigration impacting top-level power grids. Experience working with large power nets and hierarchical analysis methodologies to balance accuracy and runtime efficiency in EM/IR signoff. Experience with IP-level power integrity collateral and quality assurance for EM/IR at the SoC level. Familiarity with power-up sequencing, in-rush current management, and ESD considerations in SoC PDN design. Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, You Can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement. I'm interested Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, You Can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement. Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, You Can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what’s next in electronics and the world. Job Description Key Responsibilities Lead EM/IR analysis and closure efforts at SoC/top-level, focusing on power grid robustness, EM reliability, and IR drop minimization across complex multi-block subsystems. Architect and evolve EM/IR methodologies and PNR strategies tailored for top-level power nets, integrating thermal-aware and hierarchical analysis techniques. Drive automation and development of EM/IR signoff flows, including integration with parasitic extraction, thermal maps, and advanced simulation tools. Provide technical leadership and mentorship to engineering teams, promoting best practices in EM/IR analysis, PNR integration, and power integrity closure. Collaborate cross-functionally with physical design, timing, and verification teams to resolve EM/IR-related design challenges and optimize power delivery network performance. Communicate complex technical findings clearly to senior management and customers, influencing design and reliability decisions at the SoC level. Qualifications 10+ years of experience specializing in Electromigration (EM) and IR drop analysis at SoC or top-level chip hierarchy, combined with strong Place and Route (PNR) background at advanced nodes (7nm, 5nm, or below). Proven expertise in full-chip and hierarchical EM/IR signoff flows, including power grid design, EM/IR-aware routing, and reliability analysis at SoC/top-level. Hands-on experience with industry-leading EM/IR and PNR tools such as Synopsys RedHawk, Cadence Voltus, Ansys PrimeX, Synopsys ICC2, Innovus, and PrimeTime. Strong scripting and automation skills (Tcl, Perl, Python) for developing and optimizing EM/IR and PNR flows at the top-level hierarchy. Deep understanding of SoC power delivery networks (PDN), EM/IR failure mechanisms, and thermal effects including Joule heating and thermomigration impacting top-level power grids. Experience working with large power nets and hierarchical analysis methodologies to balance accuracy and runtime efficiency in EM/IR signoff. Experience with IP-level power integrity collateral and quality assurance for EM/IR at the SoC level. Familiarity with power-up sequencing, in-rush current management, and ESD considerations in SoC PDN design. Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, you can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement. I'm interested Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, you can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement. Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, you can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

Hi Greetings from Eximietas Design! We are actively looking to hire Senior Analog Layout Design Engineers / Leads with 7–15 years of experience to join our growing team. 📍 Locations: Bangalore, Hyderabad & Visakhapatnam. 📅 Notice Period: 30 days or less preferred. Job Description: We’re seeking highly skilled professionals with a strong background in lower FINFET technology nodes (TSMC 5nm preferred) to contribute to cutting-edge analog layout design. Key Skills & Requirements: Expertise in IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization. Solid understanding of how layout impacts circuit performance (speed, area, etc.). Ability to implement layouts that meet tight design constraints and deliver high quality. Hands-on experience with CADENCE/SYNOPSYS layout tools and flows. Familiarity with scripting languages (PERL/SKILL) is a plus. Strong communication skills and experience working with cross-functional teams. If this opportunity interests you—or if you know someone suitable—please send your updated resume to: 📧 maruthiprasad.e@eximietas.design. Referrals are highly appreciated. We look forward to connecting with talented engineers passionate about pushing the boundaries of analog layout design! Maruthhi Naidu Talent Associate - VLSI Manager Eximietas Design - Visakhapatnam maruthiprasad.e@eximietas.design +91 8088969910.

Job Title: Physical Verification Engineer Experience: 4+Years Location: Banglaore Employment Type: Full-time Industry: Semiconductors / VLSI / ASIC Design / Foundry Job Summary: We are looking for a Physical Verification Engineer with strong expertise in physical verification flows to ensure that layouts are signoff-clean and compliant with foundry process design rules. The ideal candidate will be responsible for DRC, LVS, ERC, Antenna, and other checks across block-level and full-chip designs using industry-standard EDA tools. Key Responsibilities: Own and execute block-level and full-chip DRC , LVS , ERC , Antenna , and Density checks. Analyze physical verification violations and debug layout/schematic mismatches. Work closely with layout, circuit design, and digital backend teams to ensure verification closure. Develop and maintain PV rule decks (if applicable) and flows. Interface with foundries (e.g., TSMC, Samsung, GlobalFoundries) for rule interpretation and deck issues. Support tapeout preparation and signoff activities. Automate PV flows and improve runtime efficiency through scripting. Contribute to PV methodology development and cross-functional training. Required Skills and Experience: B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, or VLSI Design. 4+years of hands-on experience in physical verification. Strong experience with Calibre (Mentor/Siemens) or Assura/PVS (Cadence) for DRC/LVS/ERC. Familiarity with GDSII/OASIS layout formats and layout hierarchy handling. Knowledge of layout design principles and basic CMOS concepts. Good debugging and analytical skills. Scripting knowledge in Tcl , Python , or Perl for flow automation. Preferred Qualifications: Experience working at advanced technology nodes (7nm, 5nm, 3nm). Exposure to full-chip integration and signoff tapeouts. Familiarity with foundry PV rule decks and process guidelines. Knowledge of electromigration (EM), IR drop, or DFM checks is a plus. Interested can share Cv to Sharmila.b@acldigital.com

Job Title: STA & EMIR Engineer Experience: 4–15 Years Location: Pune, Hyderabad Notice Period: Immediate Joiners Preferred Job Description: We are seeking a skilled and motivated STA (Static Timing Analysis) and EMIR (Electromigration & IR Drop) Engineer with 4 to 15 years of experience in ASIC physical design verification. The ideal candidate will have strong hands-on experience in timing signoff and power integrity analysis, working across advanced process nodes. Key Responsibilities: Perform full-chip Static Timing Analysis (STA) using industry-standard tools (PrimeTime, Tempus, etc.) Drive STA signoff including constraints development, path analysis, ECO implementation, and timing closure Conduct EMIR signoff analysis using RedHawk, Voltus, or equivalent tools Analyze power grid design and provide recommendations to mitigate IR drop and electromigration issues Work closely with RTL, synthesis, and physical design teams to debug and fix timing and power integrity violations Prepare documentation and reports for timing and EMIR signoff Required Skills: Strong expertise in STA and timing closure at block and full-chip levels Solid experience in EMIR tools and analysis methodologies Good understanding of UPF/CPF-based low power designs Proficiency with tools like PrimeTime, RedHawk, Voltus, Tempus, etc. Scripting skills (TCL, Perl, Python) to automate flows Experience in advanced technology nodes (7nm, 5nm, 3nm) is a plus Education: B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or related field Preferred Attributes: Strong problem-solving skills and debugging capabilities Good communication and teamwork abilities Ability to work independently under tight timelines Immediate availability is a strong plus pls reach out to me - 8754387484/prabhu.p@acldigital.com

Hi All, Greetings from Eximietas Design...! We are hiring Senior Analog Layout Design Engineers/Leads. Experience: 4-12 years. Location: Hyderabad Job Description: ❖ Must understand techniques for managing IR drop, Electromigration, self-heating, RC delay and parasitic capacitance optimization. ❖ Understanding layout effects on the circuit such as speed and area. ❖ Ability to understand design constraints and implement high-quality layouts. ❖ Good communication skills and able to work with cross-functional teams. ❖ High level proficiency in C ADENCE/SYNOPSYS layout tools flow. ❖ Hands on experience on lower FINFET technology nodes. ❖ Scripting skills in PERL/SKILL are a plus. Interested Engineers please share your updated resume : maruthiprasad.e@eximietas.design Show more Show less

Requisition #: 15488 Our Mission: Powering Innovation That Drives Human Advancement When visionary companies need to know how their world-changing ideas will perform, they close the gap between design and reality with Ansys simulation. For more than 50 years, Ansys software has enabled innovators across industries to push boundaries by using the predictive power of simulation. From sustainable transportation to advanced semiconductors, from satellite systems to life-saving medical devices, the next great leaps in human advancement will be powered by Ansys. Innovate With Ansys, Power Your Career. Summary The Principal R&D Engineer leads the design and development of innovative solutions. In this role, the Principal R&D Engineer will act as a technical reference, working closely with customers, partners, application engineers and development teams to define and deploy major new flows, methods, and capabilities. Innovation in semiconductor design and manufacturing enables smaller device architectures with higher performance and energy efficiency for powering the smart product revolution. The physics associated with shrinking geometries, especially in the emerging 3-D IC, FinFET and stacked-die architectures, brings out design challenges related to power and reliability, affecting design closure. ANSYS simulation and modeling tools offer the sign-off accuracy and performance needed to ensure power noise integrity and reliability of even the most complex ICs, considering electromigration, thermal effects and electrostatic discharge phenomena. Responsibilities Leads the planning, architecture or research across multiple projects or disciplines Coordinates product design and development activities requiring extensive analysis in areas such as user experience, software design and solver research. Acts as a technical reference across groups or products Defines, develops, and employs best practices and maintains them through technical reviews and mentoring Performs highly complex bug verification, release testing, and beta support across multiple products. Coordinates the QA or product support teams on problems discovered and develops solutions Researches and understands the marketing requirements for products, including target environment, performance criteria and competitive issues. Works with strategic customers or proxies to assess needs and develop solutions Operates without direct supervision and functions as a high-level team leader, project manager, or software architect May be responsible for line management of a small technical team but primary duties are of an individual technical nature Minimum Qualifications BS in Engineering, Computer Science, or related field with 12 years’ experience, MS with 10 years’ experience Minimum three years of experience in EDA is must. Extensive commercial experience with enterprise software lifecycle and directing R&D projects Demonstrated leadership with a track record of delivering state-of-the-art results on complex problems Preferred Qualifications Experience in development of power integrity solutions. Demonstrated expertise in C/C++ & GPU programming, deep/machine learning algorithms Experience leading technical efforts to deliver innovative solutions that advance large-scale commercial products Proven ability to understand business requirements and translate them into software roadmaps and plans Ability to convey complex information in a clear way to stakeholders and development teams Ability to drive success across teams and geographies, and to mentor others At Ansys, we know that changing the world takes vision, skill, and each other. We fuel new ideas, build relationships, and help each other realize our greatest potential. We are ONE Ansys. We operate on three key components: our commitments to stakeholders, our values that guide how we work together, and our actions to deliver results. As ONE Ansys, we are powering innovation that drives human advancement Our Commitments Amaze with innovative products and solutions Make our customers incredibly successful Act with integrity Ensure employees thrive and shareholders prosper Our Values Adaptability: Be open, welcome what’s next Courage: Be courageous, move forward passionately Generosity: Be generous, share, listen, serve Authenticity: Be you, make us stronger Our Actions We commit to audacious goals We work seamlessly as a team We demonstrate mastery We deliver outstanding results VALUES IN ACTION Ansys is committed to powering the people who power human advancement. We believe in creating and nurturing a workplace that supports and welcomes people of all backgrounds; encouraging them to bring their talents and experience to a workplace where they are valued and can thrive. Our culture is grounded in our four core values of adaptability, courage, generosity, and authenticity. Through our behaviors and actions, these values foster higher team performance and greater innovation for our customers. We’re proud to offer programs, available to all employees, to further impact innovation and business outcomes, such as employee networks and learning communities that inform solutions for our globally minded customer base. Welcome What’s Next In Your Career At Ansys At Ansys, you will find yourself among the sharpest minds and most visionary leaders across the globe. Collectively, we strive to change the world with innovative technology and transformational solutions. With a prestigious reputation in working with well-known, world-class companies, standards at Ansys are high — met by those willing to rise to the occasion and meet those challenges head on. Our team is passionate about pushing the limits of world-class simulation technology, empowering our customers to turn their design concepts into successful, innovative products faster and at a lower cost. Ready to feel inspired? Check out some of our recent customer stories, here and here . At Ansys, it’s about the learning, the discovery, and the collaboration. It’s about the “what’s next” as much as the “mission accomplished.” And it’s about the melding of disciplined intellect with strategic direction and results that have, can, and do impact real people in real ways. All this is forged within a working environment built on respect, autonomy, and ethics. CREATING A PLACE WE’RE PROUD TO BE Ansys is an S&P 500 company and a member of the NASDAQ-100. We are proud to have been recognized for the following more recent awards, although our list goes on: Newsweek’s Most Loved Workplace globally and in the U.S., Gold Stevie Award Winner, America’s Most Responsible Companies, Fast Company World Changing Ideas, Great Place to Work Certified (China, Greece, France, India, Japan, Korea, Spain, Sweden, Taiwan, and U.K.). For more information, please visit us at www.ansys.com Ansys is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, and other protected characteristics. Ansys does not accept unsolicited referrals for vacancies, and any unsolicited referral will become the property of Ansys. Upon hire, no fee will be owed to the agency, person, or entity. Show more Show less

Looking for EMIR Engineer Job location- Pune. Exp.-5+yrs Prefer- Immediate joiner . Key Responsibilities: Perform IR drop and Electromigration (EM) analysis using tools like RedHawk, Voltus. Define EM/IR methodologies and flows. Collaborate with design teams to improve power grid design and robustness. Ensure sign-off quality results for high-performance SoCs. Create automated checks and regression flows. Required Skills: Strong knowledge of power integrity issues and reliability concerns at advanced nodes. Familiarity with power grid design, decap planning, and current estimation. Hands-on experience with EMIR tools (Ansys RedHawk, Cadence Voltus). Good knowledge of PnR flow and integration with IR/EM requirements. Regards, Sneha. Show more Show less