58 Electromigration Jobs

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Role And Responsibilities Responsible for Design and development of critical analog, mixed-signal, custom digital block, and full chip level integration support. Perform layout verification like LVS/DRC/Antenna, quality check and support documentation. Responsible for on-time delivery of block-level layouts with acceptable quality. Demonstrate leadership qualities in area/time estimation, scheduling, and execution to meet project schedule/milestones in multiple project environment. Ability to guide Peer team-members in their execution of Sub block-level layouts & review critical items. Effectively communicating with Local engineering teams to assure the success of layout project. Qualification/Requirements 2 to 6 years' experience in analog/custom layout design in advanced CMOS process, in various technology nodes (Planar, FinFET ) Expertise in Cadence VLE/VXL and Mentor Graphic Caliber DRC/LVS is a must. Should have hands on experience in creating layout of critical blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc., Good understanding of Analog Layout fundamentals (e.g., Matching, Electromigration, Latch-up, coupling, crosstalk, IR-drop, active and passive parasitic devices etc.) Understanding layout effects on the circuit such as speed, capacitance, power and area etc., Ability to understand design constraints and implement high-quality layouts. Excellent problem-solving skills in physical verification of custom layout. Multiple Tape out support experience will be an added advantage. Excellent verbal and written communication skills. About Micron Technology, Inc. We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all . With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience. To learn more, please visit micron.com/careers All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status. To request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards. Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron. AI alert : Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification. Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Role and Responsibilities Responsible for Design and development of critical analog, mixed-signal, custom digital block, and full chip level integration support. Perform layout verification like LVS/DRC/Antenna, quality check and support documentation. Responsible for on-time delivery of block-level layouts with acceptable quality. Demonstrate leadership qualities in area/time estimation, scheduling, and execution to meet project schedule/milestones in multiple project environment. Ability to guide Peer team-members in their execution of Sub block-level layouts & review critical items. Effectively communicating with Local engineering teams to assure the success of layout project. Qualification/Requirements 2 to 6 years' experience in analog/custom layout design in advanced CMOS process, in various technology nodes (Planar, FinFET ) Expertise in Cadence VLE/VXL and Mentor Graphic Caliber DRC/LVS is a must. Should have hands on experience in creating layout of critical blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc., Good understanding of Analog Layout fundamentals (e.g., Matching, Electromigration, Latch-up, coupling, crosstalk, IR-drop, active and passive parasitic devices etc.) Understanding layout effects on the circuit such as speed, capacitance, power and area etc., Ability to understand design constraints and implement high-quality layouts. Excellent problem-solving skills in physical verification of custom layout. Multiple Tape out support experience will be an added advantage. Excellent verbal and written communication skills. About Micron Technology, Inc. We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all . With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience. To learn more, please visit micron.com/careers All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status. To request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards. Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron. AI alert : Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification. Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.

As an RFIC/MMIC Layout Engineer, you will be responsible for the design, planning, scheduling, and execution of Full Chip development involving analog and digital components. Your key responsibilities will include: - Performing Full chip feasibility and die size estimation for different bonding schemes - Demonstrating expertise in floorplan design, power schemes, signal planning, routing, physical verification, and quality check - Ensuring the delivery of quality full chip layout on-schedule while meeting design intent criteria such as Speed, Capacitance, Resistance, Power, Noise, and Area - Handling complex issues and using judgment to select appropriate methods for obtaining results - Establishing strong business relationships with cross-functional teams to facilitate project execution - Collaborating closely with Synaptic Global Analog and Digital Design and CAD engineering teams Your basic qualifications for this role include: - Bachelor's degree in electrical engineering, Electronics, Physics, or a related field - Experience in RF and MMIC design, with expertise in areas such as RF switches, power amplifiers, LNA, VCO, mixers, and couplers layout Preferred skills and experience that would be beneficial for this role: - Solid understanding of active and passive devices, circuits, and electrical fundamentals - Expertise in CMOS, FDSOI, and FinFET fabrication concepts, as well as Deep Nwell and triple well processes - Proficiency in analog layout techniques, electromigration, ESD, latch-up, crosstalk, shielding, and deep sub-micron challenges - Familiarity with SOC and ASIC design flows, procedures, and deliverables - Hands-on experience with tools such as Virtuoso L/XL/GXL, Calibre, PERC, STARRC, Totem, and ESRA - Strong analytical, debugging, and problem-solving skills to resolve layout design challenges and physical verification issues - Ability to work effectively in a cross-functional and multi-site team environment across different time zones - Excellent verbal and written communication skills This job description provides a comprehensive overview of the responsibilities and qualifications required for the RFIC/MMIC Layout Engineer role.,

RFIC/MMIC Layout Engineer Roles And Responsibilities Responsible for design, planning, scheduling and execution of Full Chip development with analog and digital components. Perform Full chip feasibility and die size estimation in core limited and pad limited approach for different bonding schemes. Expertise with top to bottom and bottom to top approach floorplan, power schemes, Interface signal planning and routing, physical verification and quality check. Make sure to deliver quality full chip layout on-schedule meeting design intent - Speed, Capacitance, Resistance, Power, Noise and Area. Works on complex issues and exercises judgement in selecting methods for obtaining results. Builds strong business relationships with cross-functional teams for smoother execution of projects. Work closely with Synaptic Global Analog and Digital Design and CAD engineering teams. Basic Qualifications Bachelor’s degree in electrical engineering, Electronics, Physics, or related field. Experience with RF and MMIC design – with expertise gained in at-least one or more areas: -RF switches, power amplifiers, LNA, VCO, mixers, couplers, combiners layout. Preferred Skills And Experience Good understanding of active and passive devices, circuits and electrical fundamentals. Expert of CMOS, FDSOI and FinFET fabrication concepts, Deep Nwell and triple well process. Expert of analog layout techniques, electromigration, ESD, latch up, crosstalk, shielding and deep sub-micron challenges. Expertise with SOC and ASIC design flows, procedures and deliverables. Hands-on experience with Virtuoso L/XL/GXL (6.1.x and 12.1.x), Calibre, PERC, STARRC, Totem and ESRA tools. Strong analytical, debug and problem-solving skills in resolving layout design challenges and physical verification issues. Flexible to work in a cross functional and multi-site team environment, spanning different time zones. Must have good verbal and written communication skills.

Project description We are passionate about transforming lives through cutting-edge technology, enriching industries, communities, and the world. Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the world's most critical problems. We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way. Responsibilities Perform EMIR (Electromigration and IR drop) analysis for ASIC designs using industry-standard EDA tools such as Redhawk-SC and Redhawk IR/EM Analysis. Analyze EMIR violations and collaborate with the Physical Design (PD) team to propose and implement effective solutions. Develop and maintain automation scripts using Python, Perl, or Shell to streamline analysis and reporting processes. Work closely with cross-functional teams to support sign-off activities and ensure design closure within timelines. Document methodologies, results, and implementation options with strong clarity in both written and verbal communication. Contribute to improving existing EMIR/PD flows and explore optimizations for efficiency and scalability. Skills Must have 3-7y exp Hands-on experience in ASIC EMIR/PD flows. Expertise in EDA tools such as Redhawk-SC and Redhawk IR/EM Analysis. Proficiency in scripting languages: Python, Perl, Shell. Nice to have Knowledge of Place and Route (PnR) tools. Strong verbal and written communication skills. Familiarity with design implementation and sign-off methodologies. Other Languages English: B2 Upper Intermediate Seniority Regular Hyderabad, IN, India Req. VR-117230 Python Automotive Industry 02/09/2025 Req. VR-117230

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description We are looking for technically sound and highly skilled High-speed SERDES IO PHY Layout designer with 9-14 years of experience. Apart from Serdes PHY Layout, the ideal candidate should have a strong background in analog/IO design principles, hands-on experience with layout tools, and a passion for solving challenging technical problems. Key Responsibilities: Develop and optimize Serdes PHY, analog and mixed-signal IC layouts, ensuring high performance and manufacturability. Collaborate with design engineers to understand design requirements and translate them into precise layouts. Strong experience in debugging DRC, ERC, LVS, EMIR and PERC issues independently. Work closely with the physical design team to integrate custom blocks into the overall chip design. Identify and resolve layout-related issues, providing creative solutions to meet design specifications. Conduct design reviews and provide technical feedback to improve layout practices and methodologies. Stay up-to-date with industry trends, tools, and technologies to continuously enhance layout processes. Qualifications 9-14 years of experience in Serdes Phy, Analog and Mixed-signal IC layout design. Proficiency in layout tools such as Cadence, Synopsys, or Mentor Graphics. Hands-on experience with custom layout design for various Serdes Phy, Analog and IO circuits is required, including expertise in Bandgap references, LDOs, Clocking circuits, GPIOs, DDR IOs. Familiarity with custom digital layout (i.e. high speed logic paths). Knowledge of signal integrity issues (i.e. clock/data routes, differential routing, shielding). Strong understanding of analog/IO design principles, including circuit performance and parasitic effects. Aware of layout techniques to mitigate ESD, latch-up issues. Holds advanced knowledge of CMOS and FinFET technologies and their impact on design and performance issues in deep sub-micron process nodes, specifically 5nm and below. Experience with layout concepts that incorporate reliability considerations, including techniques for managing electromigration (EM), IR drop, and self-heating. Experience with layout optimization for power, performance, and area (PPA) metrics. Excellent problem-solving skills and attention to detail. Effective communication and teamwork abilities. Preferred Skills: Knowledge of scripting languages (e.g., Skill,TCL and SVRF) for automation tasks. Qualifications Bachelor’s or Master’s degree in Electronics or Electrical Engineering

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description We are looking for technically sound and highly skilled High-speed SERDES IO PHY Layout designer with 9-14 years of experience. Apart from Serdes PHY Layout, the ideal candidate should have a strong background in analog/IO design principles, hands-on experience with layout tools, and a passion for solving challenging technical problems. Key Responsibilities: Develop and optimize Serdes PHY, analog and mixed-signal IC layouts, ensuring high performance and manufacturability. Collaborate with design engineers to understand design requirements and translate them into precise layouts. Strong experience in debugging DRC, ERC, LVS, EMIR and PERC issues independently. Work closely with the physical design team to integrate custom blocks into the overall chip design. Identify and resolve layout-related issues, providing creative solutions to meet design specifications. Conduct design reviews and provide technical feedback to improve layout practices and methodologies. Stay up-to-date with industry trends, tools, and technologies to continuously enhance layout processes. Qualifications 9-14 years of experience in Serdes Phy, Analog and Mixed-signal IC layout design. Proficiency in layout tools such as Cadence, Synopsys, or Mentor Graphics. Hands-on experience with custom layout design for various Serdes Phy, Analog and IO circuits is required, including expertise in Bandgap references, LDOs, Clocking circuits, GPIOs, DDR IOs. Familiarity with custom digital layout (i.e. high speed logic paths). Knowledge of signal integrity issues (i.e. clock/data routes, differential routing, shielding). Strong understanding of analog/IO design principles, including circuit performance and parasitic effects. Aware of layout techniques to mitigate ESD, latch-up issues. Holds advanced knowledge of CMOS and FinFET technologies and their impact on design and performance issues in deep sub-micron process nodes, specifically 5nm and below. Experience with layout concepts that incorporate reliability considerations, including techniques for managing electromigration (EM), IR drop, and self-heating. Experience with layout optimization for power, performance, and area (PPA) metrics. Excellent problem-solving skills and attention to detail. Effective communication and teamwork abilities. Preferred Skills: Knowledge of scripting languages (e.g., Skill,TCL and SVRF) for automation tasks. Qualifications Bachelor’s or Master’s degree in Electronics or Electrical Engineering

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and highly skilled engineer committed to advancing the field of high-speed analog design. You bring a wealth of experience in designing critical analog and mixed-signal blocks, particularly for cutting-edge PCIe 6 and PCIe 7 or SerDes PHY solutions. Your technical expertise encompasses transistor-level design, deep knowledge of CMOS (including finFET and SOI processes), and a proven ability to create robust high-speed building blockssuch as LDOs, Bandgap references, ADC/DACs, PLLs, and DLLsthat consistently meet rigorous performance, power, and area targets. You thrive in collaborative, multidisciplinary environments, where your clear communication and mentoring skills empower both peers and junior engineers to excel. Your proactive approach to problem-solving and your dedication to continuous improvement ensure that you stay at the forefront of technology trends. You are adept at analyzing and mitigating jitter, maintaining signal integrity, and ensuring compliance with demanding industry standards. Your experience with porting PHY designs across technology nodes demonstrates your adaptability and commitment to delivering high-quality, innovative solutions. You value documentation, knowledge sharing, and actively contribute to a culture of learning and technical excellence. Most importantly, you are excited to join a team that values diversity, encourages bold ideas, and is committed to shaping the future of high-speed connectivity. You see challenges as opportunities and bring a growth mindset to every project you undertake. What Youll Be Doing: Designing and developing advanced analog/mixed-signal blocks for PCIe 6 and PCIe 7 PHY architectures under the guidance of senior technical leaders. Ensuring that all designs strictly adhere to PCIe protocol standards, optimizing for performance, power, and area efficiency. Porting high-speed PHY designs to various technology nodes while maintaining signal integrity and maximizing performance. Collaborating with cross-functional teamsincluding digital, verification, and layout groupsto successfully integrate analog circuits into complex SerDes PHY systems. Implementing innovative verification strategies for high-speed analog/mixed-signal circuits using state-of-the-art simulation and modeling tools. Working closely with layout teams to minimize parasitics, device stress, and process variation impacts on overall circuit performance. Analyzing simulation and silicon measurement data to validate designs and ensure compliance with PCIe standards. Mentoring junior engineers and promoting best practices in analog/mixed-signal design and verification. Documenting design features, specifications, and test methodologies for future reference and team knowledge sharing. Partnering with characterization teams to validate electrical performance of circuits in silicon and resolve technical challenges. The Impact You Will Have: Drive the development of next-generation PCIe 6 and PCIe 7 PHY designs, advancing high-speed interface technologies that power tomorrows data-driven world. Ensure Synopsys analog/mixed-signal circuits exceed industry standards, reinforcing our reputation for technical excellence and innovation. Facilitate seamless integration of analog circuits into sophisticated SerDes PHY systems, enhancing overall performance and reliability. Mentor and develop junior engineers, fostering a collaborative and innovative team environment. Lead successful porting of PHY designs across multiple technology nodes, delivering versatile and scalable solutions for diverse customer needs. Strengthen verification and validation processes, resulting in robust, reliable, and high-performing analog/mixed-signal circuits. What Youll Need: PhD with 3+ years, or MTech/MS with 7+ years of experience in analog/mixed-signal circuit design focused on high-speed interfaces such as PCIe 6/7 or SerDes PHY designs. Proven expertise in transistor-level design of high-speed analog building blocks (e.g., LDOs, Bandgap references, ADC/DACs, PLLs, DLLs). Demonstrated silicon experience in developing PHY circuits compliant with PCIe standards. Strong background in high-speed SerDes AFE development, including CTLE and CDR design. Experience designing high-speed SerDes transmitters and deep knowledge of equalization techniques (e.g., DFE, FIR filters, TX pre-emphasis). Solid foundation in jitter budgeting analysis and expertise in minimizing jitter impact on signal integrity. Experience porting PHY designs across different technology nodes and deep knowledge of CMOS, finFET, and gate-all-around processes. Comprehensive understanding of the PCIe protocol, signal integrity, jitter performance, and high-speed clocking. Ability to collaborate with layout teams to minimize parasitics, process variations, and electromigration effects. Proven track record of effective teamwork and successful project outcomes across multidisciplinary teams. Who You Are: Innovative thinker with a passion for high-speed analog design and technology advancement. Collaborative team player who values diversity and inclusion. Effective communicator, able to translate complex technical concepts to a variety of audiences. Mentor and coach, eager to support the development of junior engineers. Detail-oriented problem solver with a commitment to quality and continuous improvement. Adaptable and resourceful, thriving in fast-paced, changing environments. The Team Youll Be A Part Of: You will join a world-class analog/mixed-signal design team at Synopsys, focused on developing high-speed interface IP for next-generation semiconductor products. The team is composed of passionate engineers from diverse backgrounds, collaborating closely to deliver innovative solutions that drive the future of connectivity. Our culture emphasizes technical excellence, knowledge sharing, and continuous learning, providing an environment where your skills and ideas are valued and your career can thrive. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

Principal Analog & Mixed Signal Layout Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned professional with a deep understanding of Analog and Mixed Signal Circuit Layout, bringing at least 15 years of hands-on experience to the table. Your expertise in transistor-level analog and mixed-signal layout design is complemented by an extensive background in both CMOS and FINFET technologies. Adept in the nuances of semiconductor device physics, you approach each challenge with analytical rigor and a keen eye for detail. You thrive in dynamic, fast-paced environments and excel at managing multiple projects simultaneously while maintaining the highest quality standards. Your problem-solving abilities are second to none, and you are recognized for your self-direction and passion for continuous learning—always staying ahead of the curve with emerging technologies and layout techniques. Communication is one of your strengths; you are skilled at translating complex technical concepts for both engineering teams and management, ensuring alignment and clarity at every stage of the project. You are a collaborative leader, eager to mentor and support junior engineers, and you believe that the best results come from fostering a culture of innovation, respect, and inclusion. Your commitment to excellence and reliability drives you to deliver layouts that not only meet but exceed industry standards. If you are excited by the prospect of shaping the future of semiconductor technology and contributing to groundbreaking projects, you will find this role both challenging and rewarding. What You’ll Be Doing: Ensuring all team projects meet specifications, quality standards, and delivery milestones through rigorous oversight and guidance. Regularly reviewing layout progress and providing technology and specification-based guidelines to maintain consistency and excellence across all design blocks. Streamlining deliverable standards—layout quality, documentation, release processes—to foster a systematic and unified approach. Tracking technology and product line updates, proactively communicating changes to the execution teams and management to facilitate timely adaptations. Collaborating with cross-functional teams, including project leaders, to ensure effective project planning, estimation, and execution, and providing timely feedback to meet milestones and quality targets. Mentoring engineers, sharing best practices, and fostering a culture of continuous improvement and technical excellence within the team. The Impact You Will Have: Drive the layout design process from initial floorplanning through to project release, ensuring robust and innovative outcomes. Lead the design and development of high-quality analog and mixed-signal layouts for advanced technology nodes (2nm, 3nm, 5nm). Ensure successful implementation of CMOS and FINFET technologies, setting new benchmarks for performance and reliability. Deliver clean physical verification results through effective troubleshooting and attention to detail. Maintain high standards in layout documentation, ensuring all deliverables meet rigorous quality and deadline requirements. Manage project schedules and milestones, enabling on-time delivery and supporting the organization’s reputation for excellence. Foster innovation and success through cross-functional collaboration, driving the organization forward in the analog/mixed-signal domain. What You’ll Need: Bachelor’s or Master’s degree in Electrical Engineering or a related field. Minimum of 15+ years of experience in analog and mixed signal circuit layout. Expertise in high-speed SERDES architecture, functional block implementations, and layout design flow. Deep knowledge of the latest FinFET technology nodes across leading foundries. In-depth understanding of ESD/LU standards and their implementation in SERDES layouts. Strong grasp of reliability concepts, including electromigration, aging effects, and their impact on layout. Proficiency with EDA tools for custom mixed-signal layout flows. Solid understanding of CMOS fabrication technology and deep sub-micron effects on layout. Demonstrated passion for learning and adapting new techniques. Who You Are: A proactive leader with exceptional communication and mentoring abilities. Detail-oriented, with a relentless commitment to delivering high-quality results. Innovative, always seeking to drive technological advancement. Collaborative, excelling in teamwork across cross-functional groups. A strategic problem-solver with strong analytical and organizational skills. The Team You’ll Be A Part Of: You will be part of a dynamic and innovative layout design team focused on creating high-performance analog and mixed-signal layouts. The team is dedicated to excellence and continuous improvement, working collaboratively to achieve the organization's goals and deliver industry-leading solutions. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Principal Analog & Mixed Signal Layout Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a seasoned professional with a deep understanding of Analog and Mixed Signal Circuit Layout, bringing at least 15 years of hands-on experience to the table. Your expertise in transistor-level analog and mixed-signal layout design is complemented by an extensive background in both CMOS and FINFET technologies. Adept in the nuances of semiconductor device physics, you approach each challenge with analytical rigor and a keen eye for detail. You thrive in dynamic, fast-paced environments and excel at managing multiple projects simultaneously while maintaining the highest quality standards. Your problem-solving abilities are second to none, and you are recognized for your self-direction and passion for continuous learning—always staying ahead of the curve with emerging technologies and layout techniques. Communication is one of your strengths; you are skilled at translating complex technical concepts for both engineering teams and management, ensuring alignment and clarity at every stage of the project. You are a collaborative leader, eager to mentor and support junior engineers, and you believe that the best results come from fostering a culture of innovation, respect, and inclusion. Your commitment to excellence and reliability drives you to deliver layouts that not only meet but exceed industry standards. If you are excited by the prospect of shaping the future of semiconductor technology and contributing to groundbreaking projects, you will find this role both challenging and rewarding. What You’ll Be Doing: Ensuring all team projects meet specifications, quality standards, and delivery milestones through rigorous oversight and guidance. Regularly reviewing layout progress and providing technology and specification-based guidelines to maintain consistency and excellence across all design blocks. Streamlining deliverable standards—layout quality, documentation, release processes—to foster a systematic and unified approach. Tracking technology and product line updates, proactively communicating changes to the execution teams and management to facilitate timely adaptations. Collaborating with cross-functional teams, including project leaders, to ensure effective project planning, estimation, and execution, and providing timely feedback to meet milestones and quality targets. Mentoring engineers, sharing best practices, and fostering a culture of continuous improvement and technical excellence within the team. The Impact You Will Have: Drive the layout design process from initial floorplanning through to project release, ensuring robust and innovative outcomes. Lead the design and development of high-quality analog and mixed-signal layouts for advanced technology nodes (2nm, 3nm, 5nm). Ensure successful implementation of CMOS and FINFET technologies, setting new benchmarks for performance and reliability. Deliver clean physical verification results through effective troubleshooting and attention to detail. Maintain high standards in layout documentation, ensuring all deliverables meet rigorous quality and deadline requirements. Manage project schedules and milestones, enabling on-time delivery and supporting the organization’s reputation for excellence. Foster innovation and success through cross-functional collaboration, driving the organization forward in the analog/mixed-signal domain. What You’ll Need: Bachelor’s or Master’s degree in Electrical Engineering or a related field. Minimum of 15+ years of experience in analog and mixed signal circuit layout. Expertise in high-speed SERDES architecture, functional block implementations, and layout design flow. Deep knowledge of the latest FinFET technology nodes across leading foundries. In-depth understanding of ESD/LU standards and their implementation in SERDES layouts. Strong grasp of reliability concepts, including electromigration, aging effects, and their impact on layout. Proficiency with EDA tools for custom mixed-signal layout flows. Solid understanding of CMOS fabrication technology and deep sub-micron effects on layout. Demonstrated passion for learning and adapting new techniques. Who You Are: A proactive leader with exceptional communication and mentoring abilities. Detail-oriented, with a relentless commitment to delivering high-quality results. Innovative, always seeking to drive technological advancement. Collaborative, excelling in teamwork across cross-functional groups. A strategic problem-solver with strong analytical and organizational skills. The Team You’ll Be A Part Of: You will be part of a dynamic and innovative layout design team focused on creating high-performance analog and mixed-signal layouts. The team is dedicated to excellence and continuous improvement, working collaboratively to achieve the organization's goals and deliver industry-leading solutions. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Qualcomm India Private Limited is at the forefront of technology innovation, constantly pushing boundaries to enable next-generation experiences and drive digital transformation for a smarter, connected future. As a Qualcomm Hardware Engineer, your role involves planning, designing, optimizing, verifying, and testing electronic systems, including circuits, mechanical systems, and various other cutting-edge technologies. Collaborating with cross-functional teams, you will develop solutions to meet performance requirements for world-class products. Minimum Qualifications: - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Join the Qualcomm PMIC team, a global organization dedicated to delivering power and cost-efficient solutions for mobile, compute, AR/VR, Auto, and IoT products. As part of the new PMIC analog design team in Qualcomm Bangalore, you will contribute to Qualcomm's global PMIC design community. Key Responsibilities Include: - Leading the definition, design, verification, and documentation of mixed signal circuits and products in the Power Management field. - Implementing design and verification strategies for PMICs, focusing on a specific assigned block under supervision from a technical lead. - Conducting functionality checks on individual blocks to ensure compliance with provided specifications. - Staying up-to-date with industry trends, competitor products, and advancements in Power Management. - Involvement in all design aspects from system specification to post-silicon debug, with emphasis on layout and silicon evaluation. - Utilizing expertise in power electronics, control theory, data converters, analog front ends, and various engineering disciplines. - Leveraging design tools such as Cadence ADE, MathWorks MATLAB, Verilog/VerilogAMS, and System Verilog. - Actively contributing to next-generation initiatives and fostering innovation within the team. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, please contact disability-accommodations@qualcomm.com. Qualcomm expects all employees to adhere to applicable policies and procedures, including security and confidentiality requirements. Note to Staffing and Recruiting Agencies: Qualcomm's Careers Site is exclusively for individuals seeking job opportunities at Qualcomm. Staffing agencies and represented individuals are not authorized to use this platform for submissions. Unsolicited resumes or applications will not be accepted. For more information about this role, reach out to Qualcomm Careers directly.,

Company Description Incise Infotech Ltd is a technology company specializing in semiconductor design, IT services, and product development. The company provides services in SOC and IP verification, RTL design, virtual prototyping, memory layout design, IO layout design, analog mixed-signal design, and more. Incise Infotech invites the world's top talent to work on cutting-edge semiconductor SOCs and software solutions, aiming to produce the best practices and products to simplify life. The company's diverse expertise makes it a leader in the technology domain. Role Description This is a full-time, on-site role for a Lead Memory Layout Design Engineer located in Noida. The Lead Memory Layout Design Engineer will be responsible for designing and verifying memory layouts, working on circuit design, and ensuring the quality and functionality of analog circuits. Day-to-day tasks will include layout design, physical verification, and collaborating with other teams to optimize design processes and achieve project goals. 𝐄𝐱𝐩𝐞𝐫𝐢𝐞𝐧𝐜𝐞 : 7+ 𝐘𝐞𝐚𝐫𝐬 𝐋𝐨𝐜𝐚𝐭𝐢𝐨𝐧 : 𝐍𝐨𝐢𝐝𝐚 𝐑𝐞𝐪𝐮𝐢𝐫𝐞𝐝 𝐒𝐤𝐢𝐥𝐥𝐬 & 𝐄𝐱𝐩𝐞𝐫𝐢𝐞𝐧𝐜𝐞 : 🔹7+ years of experience in memory layout design. 🔹Strong expertise in SRAM, ROM, Register File, and other memory architectures. 🔹Proficiency with EDA tools: Cadence Virtuoso, Synopsys Custom Compiler, Mentor Graphics Calibre (DRC/LVS), etc. 🔹Solid understanding of deep sub-micron technologies (16nm, 7nm, 5nm, etc.). 🔹Knowledge of parasitic effects, IR drop, electromigration, and reliability considerations. 🔹Strong debugging, problem-solving, and teamwork skills. 𝐇𝐨𝐰 𝐭𝐨 𝐀𝐩𝐩𝐥𝐲 𝐈𝐧𝐭𝐞𝐫𝐞𝐬𝐭𝐞𝐝 𝐜𝐚𝐧𝐝𝐢𝐝𝐚𝐭𝐞𝐬 𝐜𝐚𝐧 𝐬𝐡𝐚𝐫𝐞 𝐭𝐡𝐞𝐢𝐫 𝐂𝐕 𝐚𝐭 madhuri.tomar@incise.in 𝐰𝐢𝐭𝐡 𝐭𝐡𝐞 𝐬𝐮𝐛𝐣𝐞𝐜𝐭 𝐥𝐢𝐧𝐞: 👉𝐀𝐩𝐩𝐥𝐢𝐜𝐚𝐭𝐢𝐨𝐧 𝐟𝐨𝐫 𝐌𝐞𝐦𝐨𝐫𝐲 𝐋𝐚𝐲𝐨𝐮𝐭 𝐃𝐞𝐬𝐢𝐠𝐧 𝐄𝐧𝐠𝐢𝐧𝐞𝐞𝐫 – 𝐍𝐨𝐢𝐝𝐚

www.omnidesigntech.com Principal Analog/Mixed-Signal IC Design Engineer US Based Start-up founded by Industry Veterans who have PhDs from MIT and Stanford Location: Bangalore / Hyderabad Senior Analog/Mixed-Signal Design Engineer focusing on high-performance analog-to-digital and digital-to-analog converters. The successful candidate in this role will do high performance transistor level design starting from initial specification, through design and layout supervision, silicon evaluation and characterization to final product introduction to market. Qualifications 5+ years of experience in high-performance analog or mixed-signal IC development in advanced CMOS processes Thorough familiarity with high-speed, high-resolution analog-to-digital (ADC) or digital-to-analog (DAC) data converter design techniques. Experience in designing high performance building block circuits such as bandgap reference, op-amp, comparators, oscillators, DLL, PLL etc. Must have a track record of successfully taking designs to production Must have experience with evaluating silicon on bench and familiarity with standard lab equipment Strong intuitive and analytical understanding of transistor-level circuit design including noise and mismatch analysis Experience with analog and digital behavioral modeling, and/or synthesis of digital control blocks Familiar with Cadence schematic capture, virtuoso, Spectre and/or HSPICE circuit simulation tools MATLAB understanding would be preferred but not mandatory Familiar with designing circuits for electromigration and ESD compliance in submicron CMOS process Must be familiar with layout parasitic extraction tools and layout dependent impairments in advanced CMOS processes Must be able to work independently, create and adhere to schedules Must possess strong written and verbal communication skills with an ability to work with teams spread across geographic locations Should be able to seek help proactively as well as share and pass on knowledge . we have created an exciting environment with amazing talent across multiple disciplines. We like self-motivated individuals, we encourage initiative, we look for leadership qualities, we value teamwork, we like diversity, and we reward excellence. We are looking for trailblazers to bring our vision to fruition. If you are interested in making an impact as part of a young, fast growing, cutting edge technology company, please reach out to us. We are a equal opportunity employer. We offer excellent compensation. We seek individuals that share our high standards and commitment to excellence. Contact: Uday Bhaskar Mulya Technologies "Mining the Knowledge Community" Email id : muday_bhaskar@yahoo.com

www.omnidesigntech.com Principal Analog/Mixed-Signal IC Design Engineer US Based Start-up founded by Industry Veterans who have PhDs from MIT and Stanford Location: Bangalore / Hyderabad Principal Analog/Mixed-Signal Design Engineer focusing on high-performance analog-to-digital and digital-to-analog converters. The successful candidate in this role will do high performance transistor level design starting from initial specification, through design and layout supervision, silicon evaluation and characterization to final product introduction to market. Qualifications 8+ years of experience in high-performance analog or mixed-signal IC development in advanced CMOS processes Thorough familiarity with high-speed, high-resolution analog-to-digital (ADC) or digital-to-analog (DAC) data converter design techniques. Experience in designing high performance building block circuits such as bandgap reference, op-amp, comparators, oscillators, DLL, PLL etc. Must have a track record of successfully taking designs to production Must have experience with evaluating silicon on bench and familiarity with standard lab equipment Strong intuitive and analytical understanding of transistor-level circuit design including noise and mismatch analysis Experience with analog and digital behavioral modeling, and/or synthesis of digital control blocks Familiar with Cadence schematic capture, virtuoso, Spectre and/or HSPICE circuit simulation tools MATLAB understanding would be preferred but not mandatory Familiar with designing circuits for electromigration and ESD compliance in submicron CMOS process Must be familiar with layout parasitic extraction tools and layout dependent impairments in advanced CMOS processes Must be able to work independently, create and adhere to schedules Must possess strong written and verbal communication skills with an ability to work with teams spread across geographic locations Should be able to seek help proactively as well as share and pass on knowledge . we have created an exciting environment with amazing talent across multiple disciplines. We like self-motivated individuals, we encourage initiative, we look for leadership qualities, we value teamwork, we like diversity, and we reward excellence. We are looking for trailblazers to bring our vision to fruition. If you are interested in making an impact as part of a young, fast growing, cutting edge technology company, please reach out to us. We are a equal opportunity employer. We offer excellent compensation. We seek individuals that share our high standards and commitment to excellence. Contact: Uday Bhaskar Mulya Technologies "Mining the Knowledge Community" Email id : muday_bhaskar@yahoo.com

What You ll Need: Minimum 12 years of experience in analog and mixed signal circuit layout, including at least 5 years of people management experience. Hands-on experience in complete analog layout flow from floorplanning and device placement to GDS release. Strong knowledge of electrical and electronic fundamentals, especially in FinFET node technologies. Proficiency in EDA tools for custom mixed signal layout flows. - In-depth knowledge of FinFET rules, constraints, and techniques to mitigate parasitic effects. Strong understanding of electromigration, ESD, and LUP fundamentals, with skills in analyzing EMIR, ESD PERC, and ESD CNOD results. Experience in product release flow and quality checks.

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description We are looking for technically sound and highly skilled High-speed SERDES IO PHY Layout designer with 12-15 years of experience. Apart from Serdes PHY Layout, the ideal candidate should have a strong background in analog/IO design principles, hands-on experience with layout tools, and a passion for solving challenging technical problems. Key Responsibilities: Develop and optimize Serdes PHY, analog and mixed-signal IC layouts, ensuring high performance and manufacturability. Collaborate with design engineers to understand design requirements and translate them into precise layouts. Strong experience in debugging DRC, ERC, LVS, EMIR and PERC issues independently. Work closely with the physical design team to integrate custom blocks into the overall chip design. Identify and resolve layout-related issues, providing creative solutions to meet design specifications. Conduct design reviews and provide technical feedback to improve layout practices and methodologies. Stay up-to-date with industry trends, tools, and technologies to continuously enhance layout processes. Qualifications 12-15 years of experience in Serdes Phy, Analog and Mixed-signal IC layout design. Proficiency in layout tools such as Cadence, Synopsys, or Mentor Graphics. Hands-on experience with custom layout design for various Serdes Phy, Analog and IO circuits is required, including expertise in Bandgap references, LDOs, Clocking circuits, GPIOs, DDR IOs. Familiarity with custom digital layout (i.e. high speed logic paths). Knowledge of signal integrity issues (i.e. clock/data routes, differential routing, shielding). Strong understanding of analog/IO design principles, including circuit performance and parasitic effects. Aware of layout techniques to mitigate ESD, latch-up issues. Holds advanced knowledge of CMOS and FinFET technologies and their impact on design and performance issues in deep sub-micron process nodes, specifically 5nm and below. Experience with layout concepts that incorporate reliability considerations, including techniques for managing electromigration (EM), IR drop, and self-heating. Experience with layout optimization for power, performance, and area (PPA) metrics. Excellent problem-solving skills and attention to detail. Effective communication and teamwork abilities. Preferred Skills: Knowledge of scripting languages (e.g., Skill,TCL and SVRF) for automation tasks. Qualifications Bachelor’s or Master’s degree in Electronics or Electrical Engineering Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at jobs.accommodations@sandisk.com to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.

Hi....! Greetings from Eximietas Design! We are actively looking to hire Senior Analog Layout Design Engineers / Leads with (TSMC 5nm) 5–12 years of experience to join our growing team. 📍 Locations: Hyd. 📅 Notice Period: Immediate - 30 days or Less Preferred Job Description: We’re seeking highly skilled professionals with a strong background in lower FINFET technology nodes (TSMC 5nm/7nm preferred) to contribute to cutting-edge analog layout design. Key Skills & Requirements: Expertise in IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization. Solid understanding of how layout impacts circuit performance (speed, area, etc.). Ability to implement layouts that meet tight design constraints and deliver high quality. Hands-on experience with CADENCE/SYNOPSYS layout tools and flows. Familiarity with scripting languages (PERL/SKILL) is a plus. Strong communication skills and experience working with cross-functional teams. If this opportunity interests you—or if you know someone suitable—please send your updated resume to: 📧 maruthiprasad.e@eximietas.design. Referrals are highly appreciated. We look forward to connecting with talented engineers passionate about pushing the boundaries of analog layout design! Maruthhi Naidu Talent Associate - VLSI Manager Eximietas Design - Visakhapatnam maruthiprasad.e@eximietas.design +91 8088969910.

Hi Greetings from Eximietas Design! We are actively looking to hire Senior Analog Layout Design Engineers / Leads with 7–15 years of experience to join our growing team. 📍 Locations: Hyderabad 📅 Notice Period: 30 days or less preferred. Job Description: We’re seeking highly skilled professionals with a strong background in lower FINFET technology nodes (TSMC 5nm) to contribute to cutting-edge analog layout design. Key Skills & Requirements: Expertise in IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization. Solid understanding of how layout impacts circuit performance (speed, area, etc.). Ability to implement layouts that meet tight design constraints and deliver high quality. Hands-on experience with CADENCE/SYNOPSYS layout tools and flows. Familiarity with scripting languages (PERL/SKILL) is a plus. Strong communication skills and experience working with cross-functional teams. If this opportunity interests you—or if you know someone suitable—please send your updated resume to: 📧 maruthiprasad.e@eximietas.design. Referrals are highly appreciated. We look forward to connecting with talented engineers passionate about pushing the boundaries of analog layout design! Maruthhi Naidu Talent Associate - VLSI Manager Eximietas Design - Visakhapatnam maruthiprasad.e@eximietas.design +91 8088969910.

Hi Greetings from Eximietas Design! We are actively looking to hire Senior Analog Layout Design Engineers / Leads with (TSMC 5nm preferred) 7–15 years of experience to join our growing team. 📍 Locations: Hyderabad. 📅 Notice Period: 30 days or less preferred. Job Description: We’re seeking highly skilled professionals with a strong background in lower FINFET technology nodes (TSMC 5nm/7nm preferred) to contribute to cutting-edge analog layout design. Key Skills & Requirements: Expertise in IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization. Solid understanding of how layout impacts circuit performance (speed, area, etc.). Ability to implement layouts that meet tight design constraints and deliver high quality. Hands-on experience with CADENCE/SYNOPSYS layout tools and flows. Familiarity with scripting languages (PERL/SKILL) is a plus. Strong communication skills and experience working with cross-functional teams. If this opportunity interests you—or if you know someone suitable—please send your updated resume to: 📧 maruthiprasad.e@eximietas.design. Referrals are highly appreciated. We look forward to connecting with talented engineers passionate about pushing the boundaries of analog layout design! Maruthhi Naidu Talent Associate - VLSI Manager Eximietas Design - Visakhapatnam maruthiprasad.e@eximietas.design +91 8088969910.

Hi....! Greetings from Eximietas Design! We are actively looking to hire Senior Analog Layout Design Engineers / Leads with (TSMC 5nm) 5–12 years of experience to join our growing team. 📍 Locations: Hyderabad. 📅 Notice Period: Immediate - 30 days or Less Preferred Job Description: We’re seeking highly skilled professionals with a strong background in lower FINFET technology nodes (TSMC 5nm/7nm preferred) to contribute to cutting-edge analog layout design. Key Skills & Requirements: Expertise in IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization. Solid understanding of how layout impacts circuit performance (speed, area, etc.). Ability to implement layouts that meet tight design constraints and deliver high quality. Hands-on experience with CADENCE/SYNOPSYS layout tools and flows. Familiarity with scripting languages (PERL/SKILL) is a plus. Strong communication skills and experience working with cross-functional teams. If this opportunity interests you—or if you know someone suitable—please send your updated resume to: 📧 maruthiprasad.e@eximietas.design. Referrals are highly appreciated. We look forward to connecting with talented engineers passionate about pushing the boundaries of analog layout design! Maruthhi Naidu Talent Associate - VLSI Manager Eximietas Design - Visakhapatnam maruthiprasad.e@eximietas.design +91 8088969910.

Greetings from Eximietas Design! We are currently seeking Senior Analog Layout Design Engineers/Leads with 7-15 years of experience, particularly with expertise in lower FINFET technology nodes such as TSMC 5nm/7nm. This is an exciting opportunity to join our expanding team in Visakhapatnam (Vizag) with a preferred notice period of 30 days or less. As a Senior Analog Layout Design Engineer/Lead, you will be responsible for contributing to cutting-edge analog layout design. Your key responsibilities will include optimizing IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance. You should have a solid understanding of how layout impacts circuit performance, the ability to meet tight design constraints, and deliver high-quality layouts. The ideal candidate will have hands-on experience with CADENCE/SYNOPSYS layout tools and flows. Familiarity with scripting languages such as PERL/SKILL is a plus. Additionally, strong communication skills and experience collaborating with cross-functional teams are essential for success in this role. If you are interested in this opportunity or know someone who would be a great fit, please send your updated resume to maruthiprasad.e@eximietas.design. Referrals are highly appreciated. We are excited to connect with talented engineers who are passionate about pushing the boundaries of analog layout design. We look forward to hearing from you! Maruthhi Naidu Talent Associate - VLSI Manager Eximietas Design - Visakhapatnam maruthiprasad.e@eximietas.design +91 8088969910.,

As a Hardware Testing Engineer at Google, you will play a crucial role in ensuring the reliability of Google's custom-designed machines, which form an integral part of a vast and powerful computing infrastructure. In this role, you will be responsible for designing test equipment for prototypes of cutting-edge machinery in the R&D lab and developing protocols to scale these tests for the global team. Collaborating closely with design engineers, you will provide valuable input on designs aimed at enhancing the quality and reliability of Google's hardware products. The Platforms and Devices team you will be a part of focuses on Google's diverse computing software platforms across different environments (desktop, mobile, applications) and our first-party devices and services that integrate Google AI, software, and hardware to deliver innovative user experiences worldwide. Your responsibilities will include working with post-silicon validation teams to enhance and troubleshoot speed, Vmin, and yield-related issues. You will also collaborate with cross-functional teams involving circuit design, physical design, and sign-off methodology to drive innovation and improvements in circuit/Static Timing Analysis methodologies for advanced subsystems and System on a Chip (SoCs). Additionally, you will work with testchip teams on process nodes to construct, validate, and characterize custom Internet Protocols (IPs) and develop automation for circuit methodology, simulation, and analysis. Your role will be pivotal in ensuring the performance, reliability, and quality of Google's hardware products, thereby contributing to the seamless and efficient computing experiences for users globally.,

As an Analog Layout Engineer with 3-5 years of experience in advanced semiconductor technologies (5nm and below), you will be responsible for executing full custom layout designs for high-speed analog and mixed-signal blocks. Your expertise in custom layout design, FinFET technology nodes, and EDA tools like Cadence Virtuoso and Calibre will be crucial in collaborating closely with circuit design teams to interpret and implement layout specifications. Your key responsibilities will include performing layout verification, ensuring compliance with foundry design rules and layout best practices, addressing issues related to electromigration, IR drop (EMIR), and layout-dependent effects, as well as optimizing layouts for performance, area, and reliability across PVT corners. Additionally, you will support tape-out and post-layout verification activities, participate in design reviews, and maintain proper documentation of layout guidelines and review skills. You should have proven experience in custom analog layout for high-speed and precision circuits, a strong working knowledge of FinFET nodes, proficiency in layout tools like Cadence Virtuoso and Calibre, and sound knowledge of DRC, LVS, and EMIR verification methodologies. Understanding of layout effects such as matching, shielding, symmetry, and noise isolation, as well as familiarity with EDA scripting (Skill, Tcl, Python), will be beneficial. Strong problem-solving skills, attention to detail, and good communication and collaboration abilities in a team-based environment are essential for success in this role. Join us to work on cutting-edge layout challenges with the latest process technologies and be a part of a fast-growing semiconductor team working on impactful silicon designs. Competitive compensation and career development opportunities await you in this exciting opportunity.,

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Role and Responsibilities Highly motivated with passion, detail oriented, systematic and methodical approach in IC layout design Perform layout verification like LVS/DRC/Antenna, quality check and documentation. Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment. Lead the layout design and development of complex analog, mixed-signal, and digital blocks and full chip level integration Ensure timely delivery of high-quality block-level layouts, meeting project milestones and design specifications. Perform layout verification including LVS, DRC, and antenna checks, along with thorough quality reviews and documentation. Collaborate with global engineering teams to ensure successful execution and integration of layout projects. Provide technical guidance and mentorship to junior team members, reviewing sub-block layouts and supporting their development. Demonstrate leadership in planning, time estimation, scheduling, and execution across multiple projects. Contribute actively to project management and cross-functional coordination. Proven experience in IC layout design with a systematic and methodical approach. Strong attention to detail and a passion for high-quality design. Excellent communication and collaboration skills, especially in a global team environment. Ability to manage multiple priorities and deliver results under tight timelines. Qualification/Requirements 8 to 15 years' experience in analog/custom layout design in advanced CMOS process, in various technology nodes (Planar, FinFET ) Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must. Should have hands on experience in creating layout of critical blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc., Good understanding of Analog Layout fundamentals (e.g., Matching, Electro-migration, Latch-up, coupling, crosstalk, IR-drop, active and passive parasitic devices etc.) Understanding layout effects on the circuit such as speed, capacitance, power and area etc., Ability to understand design constraints and implement high-quality layouts. Ability to understand design hierarchy and different architectures for Memory designs. Excellent command and problem-solving skills in physical verification of custom layout. Multiple Tape out support experience will be an added advantage. Experience in managing multiple layout projects, ensuring quality checks are taken care at all stages of layout development. Excellent verbal and written communication skills. Experience: 8–15 years in analog/custom layout design across advanced CMOS process nodes, including Planar and FinFET technologies. Tool Proficiency: Strong expertise in Cadence VLE/VXL and Mentor Graphics Calibre for DRC/LVS verification is essential. Technical Expertise: Hands-on experience in layout design of critical analog and mixed-signal blocks such as: Temperature Sensors, PLLs, ADCs, DACs, LDOs, Bandgaps, Reference Generators, Charge Pumps, Current Mirrors, Comparators, and Differential Amplifiers. Fundamentals: Solid understanding of analog layout principles including matching, electromigration, latch-up, coupling, crosstalk, IR-drop, and parasitic effects. Design Awareness: Ability to assess and mitigate layout impacts on circuit performance—speed, capacitance, power, and area. Memory Architecture: Familiarity with design hierarchies and memory layout architectures is a plus. Verification Skills: Strong problem-solving skills in physical verification and debugging of custom layouts. Tapeout Experience: Prior involvement in multiple successful tapeouts is highly desirable. Project Management: Proven ability to manage multiple layout projects, ensuring quality and timely delivery at all stages. Communication: Excellent verbal and written communication skills, with the ability to collaborate effectively across global teams. Education BE or MTech in Electronic/VLSI Engineering All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status. About Micron Technology, Inc. We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all . With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience. To learn more, please visit micron.com/careers All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status. To request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards. Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron. AI alert : Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification. Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.

Greetings from Eximietas Design! We are actively looking to hire Senior Analog Layout Leads/Architects with 7-15 years of experience in lower FINFET technology nodes, preferably TSMC 5nm, to join our growing team in Hyderabad. We prefer candidates with a notice period of 30 days or less. As a Senior Analog Layout Lead/Architect, you will be responsible for contributing to cutting-edge analog layout design. You should have expertise in IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance optimization. A solid understanding of how layout impacts circuit performance, such as speed and area, is essential. You should be able to implement layouts that meet tight design constraints while delivering high quality results. Hands-on experience with CADENCE/SYNOPSYS layout tools and flows is required, and familiarity with scripting languages like PERL/SKILL is a plus. Strong communication skills are necessary as you will be working with cross-functional teams. If you are interested in this opportunity or know someone who would be suitable, please send your updated resume to maruthiprasad.e@eximietas.design. Referrals are highly appreciated. We look forward to connecting with talented engineers who are passionate about pushing the boundaries of analog layout design! Maruthhi Naidu Talent Associate - VLSI Manager Eximietas Design - Visakhapatnam maruthiprasad.e@eximietas.design +91 8088969910.,