Job
Description
Harman International is seeking highly driven and self-motivated RTL Design Engineers to join our cutting-edge semiconductor design team in Bangalore. This is a critical engineering role focused on synthesis, logic equivalence checking (LEC), and constraint development for high-performance digital IPs. You will be responsible for collaborating closely with architects, RTL developers, and other cross-functional teams to implement industry-standard design flows and methodologies. Responsibilities The ideal candidate is someone who has a strong understanding of physical design-aware synthesis, timing analysis, floor planning, and power optimization for advanced SoC and IP-level designs. Were looking for individuals who thrive in a fast-paced environment, are capable of taking full ownership of their deliverables, and can work independently with minimal Responsibilities : Collaborate with RTL designers and chip architects to implement synthesis, LEC (logic equivalence checks), and SDC (Synopsys Design Constraints) for NXPs digital IP designs. Own and drive physical-aware synthesis flows, including floorplanning and power/performance trade-off analysis for high-performance IPs. Perform timing and power analysis on the database (db), improve timing closure strategies, and provide actionable feedback to RTL and verification teams. Conduct timing signoff and static timing analysis (STA) using industry tools such as Primetime. Establish and maintain flow automation scripts for synthesis and LEC to support robust design delivery processes. Create and maintain design recipes to optimize timing, area, and power, ensuring delivery meets project milestones and design targets. Communicate effectively with cross-functional team members including verification, physical design, and program management to ensure smooth project execution. Take ownership as an individual contributor or lead engineer on specific IPs or subsystems, managing synthesis schedules and task breakdowns. Deliver weekly project status reports, capturing progress, challenges, and metrics around timing closure, synthesis QoR (Quality of Results), and tool flow efficiency. Desired Skills And Experience Experience : 3 to 12 years of relevant industry experience in RTL synthesis, LEC, and timing constraint development at the IP or SoC level. Strong understanding of synthesis flows, including setup from scratch and working with large-scale digital designs. Proficiency in using synthesis tools such as Synopsys Fusion Compiler, Design Compiler, or Cadence Genus. Hands-on experience with floorplanning, power optimization, and constraint development for advanced node designs (7nm/5nm/FinFET preferred). Solid understanding of timing analysis, multi-mode/multi-corner analysis, and power/timing closure methodologies. Practical knowledge of LEC tools like Conformal or Formality for equivalence checking. Familiarity with P&R (Place and Route) flow concepts and their influence on synthesis and timing constraints. Scripting expertise in TCL, Perl, and Python to automate design flows and reporting. Exposure to industry tools like Primetime, Innovus, and IC Compiler. Ability to work independently or as a team lead with minimal supervision and clear accountability for deliverables. Strong documentation and communication skills to maintain flow manuals and collaborate across geographically distributed teams. Preferred Qualifications Bachelor's or Masters degree in Electronics and Communication Engineering, VLSI Design, Computer Engineering, or a related field. Exposure to advanced SoC design and verification environments. Experience working in product companies or semiconductor IDMs will be considered a plus. (ref:hirist.tech) Show more Show less
