Design for Testability (DFT) Engineer (5-8 years’ experience)
Company:
Job Summary:
We are seeking a highly motivated and experienced DFT Engineer to join our team and play a crucial role in ensuring the testability and manufacturability of our complex ASICs and SoCs. This position requires a strong understanding of DFT methodologies and the ability to independently implement and optimize DFT strategies. You will be responsible for collaborating with design and verification teams to achieve high test coverage and manufacturability goals for our next-generation integrated circuits.
Responsibilities:
- Collaborate with design and verification engineers throughout the design flow to integrate DFT techniques
- Develop and implement comprehensive DFT strategies, including scan insertion, Automatic Test Pattern Generation (ATPG), and Boundary Scan (JTAG) insertion
- Utilize advanced DFT tools and methodologies to achieve high test coverage and fault detection rates
- Analyze test results, identify potential design issues, and recommend corrective actions
- Develop and maintain DFT test plans and reports, ensuring adherence to industry standards
- Participate in design reviews and provide expert guidance on DFT feasibility and optimization
- Stay current with the latest advancements in DFT tools, methodologies, and industry best practices
- Contribute to the continuous improvement of the DFT flow within the team
Qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus)
- 5-8 years of solid experience in Design for Testability (DFT) for ASICs or SoCs
- In-depth knowledge of DFT concepts (scan insertion, ATPG, BSCAN, fault modeling, test coverage analysis)
- Proven ability to independently implement and optimize DFT strategies
- Expertise in industry-standard DFT tools (Synopsys DFT Compiler, TetraMAX, etc.)
- Experience with scripting languages (Perl, TCL) for automation is a plus
- Strong understanding of digital design principles (combinational logic, sequential logic)
- Excellent analytical and problem-solving skills with a focus on achieving high test quality
- Effective communication, collaboration, and teamwork skills
Benefits:
- Competitive salary and benefits package commensurate with experience
- Opportunity to work on leading-edge technologies and complex projects
- Collaborative and dynamic work environment with opportunities for professional growth
- Recognition and rewards for outstanding contributions
Design for Testability (DFT) Engineer (Senior Level - 10+ years’ experience)
Company:
Job Summary:
We are seeking a highly accomplished Design for Testability (DFT) Engineer to join our elite team and lead the DFT efforts for our most critical ASIC and SoC projects. This senior-level position demands a mastery of DFT methodologies and the ability to drive the implementation of robust test strategies. You will play a pivotal role in ensuring the manufacturability and high-quality testing of our next-generation integrated circuits.
Responsibilities:
- Lead and define the overall DFT strategy for assigned projects, considering manufacturability, test coverage, and cost optimization
- Collaborate with design and verification teams throughout the design flow to seamlessly integrate DFT techniques
- Develop and implement advanced DFT methodologies (scan insertion, ATPG, Boundary Scan, Design for X) to achieve exceptional test coverage and fault detection rates
- Champion best practices for DFT and actively participate in design reviews, providing expert guidance on DFT feasibility and optimization
- Lead and mentor junior DFT engineers, fostering a culture of excellence and knowledge sharing within the team
- Analyze test results, identify potential design issues, and recommend corrective actions to ensure high test quality
- Stay at the forefront of the DFT landscape by actively researching and adopting emerging tools and methodologies
- Manage and maintain DFT libraries and internal DFT standards
- Contribute to the continuous improvement of the DFT flow within the team
Qualifications:
- Master's degree in Electrical Engineering, Computer Engineering, or a related field (highly preferred)
- Minimum of 10+ years of experience in Design for Testability (DFT) for complex ASICs and SoCs
- Proven track record of successfully leading and implementing DFT strategies for high-volume production
- In-depth knowledge of advanced DFT concepts (scan insertion, ATPG, Boundary Scan, Design for Reliability, Design for Power, etc.)
- Expertise in industry-standard DFT tools (Synopsys DFT Compiler, TetraMAX, etc.) and scripting languages (Perl, TCL) for automation
- Strong understanding of digital design principles (combinational logic, sequential logic) and manufacturing test processes
- Excellent analytical and problem-solving skills with a focus on achieving optimal test quality and cost-effectiveness
- Effective leadership, communication, collaboration, and teamwork skills
Benefits:
- Competitive salary and benefits package commensurate with experience and expertise
- Opportunity to lead and influence the DFT strategy for cutting-edge technologies
- Dynamic and challenging work environment with opportunities for professional growth and leadership development
- Recognition and rewards for outstanding contributions
