Director - Physical Design

Company Description

Tecquire Solutions Private Limited is a comprehensive provider of semiconductor design services. The company was founded by a team with over 25+ years of experience in the semiconductor industry. Tecquire Solutions provides tailored services in the areas of DFT architecture, DFT implementation, silicon debug, pattern reduction, and Netlist to GDSII implementation. The company has a strong track record of successful SOC design and first-time silicon success across multiple tape-outs.

Job Summary:

Director of Physical Design

Key Responsibilities:

• Lead and manage the entire Physical Design team across multiple projects and geographies.
• Drive end-to-end physical implementation: RTL handoff, floorplanning, place & route, clock tree synthesis, static timing analysis, physical verification (DRC/LVS), and tape-out.
• Own project planning, resource allocation, schedule management, and risk mitigation across multiple physical design programs.
• Collaborate with RTL, DFT, Verification, Packaging, and Process Technology teams to ensure successful chip integration and delivery.
• Define and enforce design methodologies, flows, and best practices to improve quality, efficiency, and tape-out success.
• Interface with EDA vendors to evaluate tools and improve tool flow and performance.
• Ensure design goals are met for power, performance, area (PPA), and yield.
• Hire, mentor, and develop a high-performing team of engineers and managers.
• Contribute to technology planning and roadmap discussions in alignment with product strategy.

Requirements:

Education & Experience:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field (PhD preferred).
• 15+ years of experience in VLSI/ASIC/SoC physical design, with at least 5-6 years in a leadership or director-level role.
• Proven experience in leading full-chip physical design to successful tape-out at advanced process nodes (e.g., 7nm, 5nm, 3nm).

Technical Skills:

• Deep understanding of physical design flow and EDA tools (Cadence, Synopsys, Mentor, etc.).
• Strong expertise in STA, low-power design, DFT integration, IR drop analysis, EM, and signal integrity.
• Experience with hierarchical physical design methodologies and large SoC integration.
• Knowledge of advanced packaging (e.g., chiplets, 2.5D/3D IC) is a plus.

Leadership & Communication:

• Proven ability to lead large teams and manage complex multi-disciplinary projects.
• Strong interpersonal and communication skills; able to influence across teams and executive stakeholders.
• Track record of mentoring and developing high-performing teams.

Preferred Qualifications:

• Experience in working with foundries like TSMC, Samsung, Intel Foundry.
• Familiarity with ISO 26262, functional safety, or security standards (for automotive or safety-critical applications).
• Exposure to ML/AI acceleration, networking, or mobile SoC designs is an advantage.

Why Join Us:

• Opportunity to shape next-generation semiconductor products.
• Collaborative and innovation-driven culture.
• Competitive compensation and stock options.
• Work on cutting-edge technology with world-class engineering teams.